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Features
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Compatible with MCS(R)-51 Products 20K Bytes of Reprogrammable Flash Memory Endurance: 1000 Write/Erase Cycles 4V to 5.5V Operating Range Fully Static Operation: 0 Hz to 33 MHz Three-level Program Memory Lock 256 x 8-bit Internal RAM 32 Programmable I/O Lines Three 16-bit Timer/Counters Eight Interrupt Sources Programmable Serial Channel Low-power Idle and Power-down Modes Interrupt Recovery from Power-down Mode Hardware Watchdog Timer Dual Data Pointer Power-off Flag
8-bit Microcontroller with 20K Bytes Flash AT89C55WD
Description
The AT89C55WD is a low-power, high-performance CMOS 8-bit microcontroller with 20K bytes of Flash programmable read only memory and 256 bytes of RAM. The device is manufactured using Atmel's high-density nonvolatile memory technology and is compatible with the industry standard 80C51 and 80C52 instruction set and pinout. The on-chip Flash allows the program memory to be user programmed by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C55WD is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. The AT89C55WD provides the following standard features: 20K bytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector, two-level interrupt architecture, a full-duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89C55WD is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.
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Pin Configurations
TQFP
P1.4 P1.3 P1.2 P1.1 (T2 EX) P1.0 (T2) NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22
P1.5 P1.6 P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5
1 2 3 4 5 6 7 8 9 10 11
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
(T2) P1.0 (T2EX) P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND
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(WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND NC (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4
18 19 20 21 22 23 24 25 26 27 28
P1.5 P1.6 P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5
7 8 9 10 11 12 13 14 15 16 17
6 5 4 3 2 1 44 43 42 41 40
P1.4 P1.3 P1.2 P1.1 (T2 EX) P1.0 (T2) NC VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) 39 38 37 36 35 34 33 32 31 30 29 P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
(WR) P3.6 (RD) P3.7 XTAL2 XTAL1 GND GND (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4
PDIP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8)
PLCC
AT89C55WD
Block Diagram
P0.0 - P0.7 P2.0 - P2.7
VCC PORT 0 DRIVERS GND PORT 2 DRIVERS
RAM ADDR. REGISTER
RAM
PORT 0 LATCH
PORT 2 LATCH
QUICK FLASH
B REGISTER
ACC
STACK POINTER
PROGRAM ADDRESS REGISTER
TMP2
TMP1
BUFFER
ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS
PC INCREMENTER
PSW
PROGRAM COUNTER
PSEN ALE/PROG EA / VPP RST PORT 1 LATCH PORT 3 LATCH TIMING AND CONTROL INSTRUCTION REGISTER DUAL DPTR
WATCH DOG
OSC PORT 1 DRIVERS PORT 3 DRIVERS
P1.0 - P1.7
P3.0 - P3.7
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Pin Description
VCC GND Port 0 Supply voltage. Ground. Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups. Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pull-ups are required during program verification. Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table. Port 1 also receives the low-order address bytes during Flash programming and verification.
Port Pin P1.0 P1.1 Alternate Functions T2 (external count input to Timer/Counter 2), clock-out T2EX (Timer/Counter 2 capture/reload trigger and direction control)
Port 2
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pull-ups. Port 3 receives some control signals for Flash programming and verification. Port 3 also serves the functions of various special features of the AT89C55WD, as shown in the following table.
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Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7
Alternate Functions RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (timer 0 external input) T1 (timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe)
RST
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled. Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
ALE/PROG
PSEN
Program Store Enable is the read strobe to external program memory. When the AT89C55WD is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
EA/VPP
External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12V programming enable voltage (VPP) during Flash programming.
XTAL1 XTAL2
Input to the inverting oscillator amplifier and input to the internal clock operating circuit. Output from the inverting oscillator amplifier.
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Table 1. AT89C55WD SFR Map and Reset Values
0F8H 0F0H 0E8H 0E0H 0D8H 0D0H 0C8H 0C0H 0B8H 0B0H 0A8H 0A0H 98H 90H 88H 80H IP XX000000 P3 11111111 IE 0X000000 P2 11111111 SCON 00000000 P1 11111111 TCON 00000000 P0 11111111 TMOD 00000000 SP 00000111 TL0 00000000 DP0L 00000000 TL1 00000000 DP0H 00000000 TH0 00000000 DP1L 00000000 TH1 00000000 DP1H 00000000 AUXR XXX00XX0 PCON 0XXX0000 SBUF XXXXXXXX AUXR1 XXXXXXX0 WDTRST XXXXXXXX PSW 00000000 T2CON 00000000 T2MOD XXXXXX00 RCAP2L 00000000 RCAP2H 00000000 TL2 00000000 TH2 00000000 ACC 00000000 B 00000000 0FFH 0F7H 0EFH 0E7H 0DFH 0D7H 0CFH 0C7H 0BFH 0B7H 0AFH 0A7H 9FH 97H 8FH 87H
Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 2) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.
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Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register. Table 2. T2CON--Timer/Counter 2 Control Register
T2CON Address = 0C8H Bit Addressable Bit TF2 7 EXF2 6 RCLK 5 TCLK 4 EXEN2 3 TR2 2 C/T2 1 CP/RL2 0 Reset Value = 0000 0000B
Table 3. AUXR: Auxiliary Register
AUXR Address = 8EH Not Bit Addressable - Bit 7 - 6 - 5 WDIDLE 4 DISRTO 3 - 2 - 1 DISALE 0 Reset Value = XXX00XX0B
- DISALE
Reserved for future expansion Disable/Enable ALE DISALE 0 1 Operating Mode ALE is emitted at a constant rate of 1/6 the oscillator frequency ALE is active only during a MOVX or MOVC instruction
DISRTO
Disable/Enable Reset out DISRTO 0 1 Operating Mode Reset pin is driven High after WDT times out Reset pin is input only
WDIDLE
Disable/Enable WDT in IDLE mode WDIDLE 0 1 Operating Mode WDT continues to count in IDLE mode WDT halts counting in IDLE mode
Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register. Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to "1" during power up. It can be set and rest under software control and is not affected by reset.
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Table 4. AUXR1: Auxiliary Register 1
AUXR1 Address = A2H Not Bit Addressable - Bit 7 - 6 - 5 - 4 - 3 - 2 - 1 DPS 0 Reset Value = XXXXXXX0B
- DPS
Reserved for future expansion Data Pointer Register Select DPS 0 1 Selects DPTR Registers DP0L, DP0H Selects DPTR Registers DP1L, DP1H
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Memory Organization
Program Memory
MCS-51 devices have a separate address space for Program and Data Memory. Up to 64 Kbytes each of external Program and Data Memory can be addressed. If the EA pin is connected to GND, all program fetches are directed to external memory. On the AT89C55WD, if EA is connected to VCC, program fetches to addresses 0000H through 4FFFH are directed to internal memory and fetches to addresses 5000H through FFFFH are to external memory.
Data Memory
The AT89C55WD implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space. For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).
MOV @R0, #data
Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.
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Hardware Watchdog Timer (One-time Enabled with Reset-out) Using the WDT
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 13-bit counter and the WatchDog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT time-out period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.
To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 13-bit counter overflows when it reaches 8191 (1FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 8191 machine cycles. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. In Power-down mode the oscillator stops, which means the WDT also stops. While in Powerdown mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89C55WD is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down. To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down. Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89C55WD while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter IDLE mode. With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.
WDT During Power-down and Idle
UART
The UART in the AT89C55WD operates the same way as the UART in the AT89C51 and AT89C52. For further information, see the December 1997 Microcontroller Data Book, page 248, section titled, "Serial Interface".
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Timer 0 and 1 Timer 2
Timer 0 and Timer 1 in the AT89C55WD operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 2. Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.
Table 5. Timer 2 Operating Modes
RCLK +TCLK 0 0 1 X CP/RL2 0 1 X X TR2 1 1 1 0 MODE 16-bit Auto-Reload 16-bit Capture Baud Rate Generator (Off)
In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.
Capture Mode
In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illustrated in Figure 5. Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 6). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.
Auto-reload (Up or Down Counter)
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Figure 5. Timer in Capture Mode
OSC /12 C/T2 = 0 TH2 CONTROL C/T2 = 1 T2 PIN TRANSITION DETECTOR T2EX PIN CONTROL EXEN2 EXF2 TR2 CAPTURE RCAP2H RCAP2L TIMER 2 INTERRUPT TL2 TF2 OVERFLOW
Figure 6 shows Timer 2 automatically counting up when DCEN=0. In this mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled. Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 6. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively. A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers. The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.
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Figure 6. Timer 2 Auto Reload Mode (DCEN = 0)
OSC /12 C/T2 = 0 TH2 CONTR OL TR2 C/T2 = 1 T2 PIN RCAP2H RCAP2L TF2 TRANSITION DETECTOR T2EX PIN CONTROL EXEN2 EXF2 RELO AD TIMER 2 INTERRUPT TL2 OVERFLOW
Table 6. T2MOD - Timer 2 Mode Control Register
T2MOD Address = 0C9H Not Bit Addressable - Bit 7 - 6 - 5 - 4 - 3 - 2 T2OE 1 DCEN 0 Reset Value = XXXX XX00B
Symbol - T2OE DCEN
Function Not implemented, reserved for future Timer 2 Output Enable bit When set, this bit allows Timer 2 to be configured as an up/down counter
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Figure 7. Timer 2 Auto Reload Mode (DCEN = 1)
(DOWN COUNTING RELOAD VALUE)
0FFH 0FFH TOGGLE EXF2
OSC
/ 12
C/T2 = 0 TH2 CONTROL TR2 C/T2 = 1 T2 PIN TL2
OVERFLOW
TF2
TIMER 2 INTERRUPT
RCAP2H RCAP2L
(UP COUNTING RELOAD VALUE)
COUNT DIRECTION 1=UP 0=DO
T2EX PIN
Figure 8. Timer 2 in Baud Rate Generator Mode
TIMER 1 OVERFLOW
/2
"0" NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12 SMOD1 OSC "1"
/2
C/T2 = 0 "1" TH2 CONTROL TR2 C/T2 = 1 "1" "0" TCLK Tx CLOCK TL2 RCLK "0" Rx CLOCK
/ 16
T2 PIN RCAP2H RCAP2L TRANSITION DETECTOR T2EX PIN CONTROL EXEN2 EXF2 TIMER 2 INTERRUPT
/ 16
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Baud Rate Generator
Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table 2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 8. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. The baud rates in Modes 1 and 3 are determined by Timer 2's overflow rate according to the following equation.
Timer 2 Overflow Rate Modes 1 and 3 Baud Rates = ----------------------------------------------------------16
The Timer can be configured for either timer or counter operation. In most applications, it is configured for timer operation (CP/T2 = 0). The timer operation is different for Timer 2 when it is used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). The baud rate formula is given below.
Modes 1 and 3 Oscillator Frequency -------------------------------------- = ------------------------------------------------------------------------------------Baud Rate 32 x [65536-RCAP2H,RCAP2L)]
where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. Timer 2 as a baud rate generator is shown in Figure 8. This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an interrupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt. Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.
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Figure 9. Timer 2 in Clock-Out Mode
OSC 2 TL2 (8-BITS) TH2 (8-BITS)
TR2
RCAP2L RCAP2H C/T2 BIT
P1.0 (T2)
2
T2OE (T2MOD.1) TRANSITION DETECTOR P1.1 (T2EX) TIMER 2 INTERRUPT
EXF2
EXEN2
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Programmable Clock Out
A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 9. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz for a 16 MHz operating frequency. To configure the Timer/Counter 2 as a clock generator, bit C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer. The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation.
Oscillator Frequency Clock-Out Frequency = -----------------------------------------------------------------------------------4 x [65536-(RCAP2H,RCAP2L)]
In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and clockout frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L.
Interrupts
The AT89C55WD has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 10. Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once. Note that Table 5 shows that bit position IE.6 is unimplemented. User software should not write a `1' to this bit position, since it may be used in future AT89 products. Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software. The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.
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1921B-MICRO-09/02
Table 7. Interrupt Enable (IE) Register
(MSB) EA (LSB)
-
ET2
ES
ET1
EX1
ET0
EX0
Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables the interrupt.
Symbol EA
Position IE.7
Function Disables all interrupts. If EA = 0, no interrupt is acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Reserved. Timer 2 interrupt enable bit. Serial Port interrupt enable bit. Timer 1 interrupt enable bit. External interrupt 1 enable bit. Timer 0 interrupt enable bit. External interrupt 0 enable bit.
- ET2 ES ET1 EX1 ET0 EX0
IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0
User software should never write 1s to reserved bits, because they may be used in future AT89 products.
Figure 10. Interrupt Sources
0 INT0 1 IE0
TF0
0 INT1 1 IE1
TF1 TI RI TF2 EXF2
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1921B-MICRO-09/02
AT89C55WD
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 11. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 12. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.
Idle Mode
Power-down Mode
In the Power-down mode, the oscillator is stopped, and the instruction that invokes Powerdown is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down can be initiated either by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. Figure 11. Oscillator Connections
C2 XTAL2
C1 XTAL1
GND
Note:
C1, C2 = 30 pF 10 pF for Crystals = 40 pF 10 pF for Ceramic Resonators
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1921B-MICRO-09/02
Figure 12. External Clock Drive Configuration
NC XTAL2
EXTERNAL OSCILLATOR SIGNAL
XTAL1
GND
Table 8. Status of External Pins During Idle and Power-down Modes
Mode Idle Idle Power-down Power-down Program Memory Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT0 Data Float Data Float PORT1 Data Data Data Data PORT2 Data Address Data Data PORT3 Data Data Data Data
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1921B-MICRO-09/02
AT89C55WD
Program Memory Lock Bits
The AT89C55WD has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the following table. Table 9. Lock Bit Protection Modes
Program Lock Bits LB1 1 U LB2 U LB3 U Protection Type No program lock features. MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash memory is disabled. Same as mode 2, but verify is also disabled. Same as mode 3, but external execution is also disabled.
2
P
U
U
3 4
P P
P P
U P
When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The latched value of EA must agree with the current logic level at that pin in order for the device to function properly.
Programming the Flash
The AT89C55WD is shipped with the on-chip Flash memory array ready to be programmed. The programming interface needs a high-voltage (12-volt) program enable signal and is compatible with conventional third-party Flash or EPROM programmers. The AT89C55WD code memory array is programmed byte-by-byte. Programming Algorithm: Before programming the AT89C55WD, the address, data, and control signals should be set up according to the Flash programming mode table and Figures 13 and 14. To program the AT89C55WD, take the following steps: 1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The bytewrite cycle is self-timed and typically takes no more than 50 s. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Chip Erase Sequence: Before the AT89C55WD can be reprogrammed, a Chip Erase operation needs to be performed. To erase the contents of the AT89C55WD, follow this sequence: 1. Raise VCC to 6.5V. 2. Pulse ALE/PROG once (duration of 200 - 500 ns). 3. Wait for 150 ms. 4. Power VCC down and up to 6.5V. 5. Pulse ALE/PROG once (duration of 200 - 500 ns). 6. Wait for 150 ms. 7. Power VCC down and up to 6.5V. Data Polling: The AT89C55WD features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written data on P0.7. Once the write cycle has been completed, true data is valid on all out21
1921B-MICRO-09/02
puts, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY. P3.0 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The status of the individual lock bits can be directly verified by reading them back. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows: (000H) = 1EH indicates manufactured by Atmel (100H) = 55H (200H) = 06H indicates 89C55WD
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AT89C55WD
Programming Interface
Every code byte in the Flash array can be programmed by using the appropriate combination of control signals. The write operation cycle is self-timed and once initiated, will automatically time itself to completion. Most worldwide major programming vendors offer support for the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision. Table 10. Flash Programming Modes
Mode Write Code Data Read Code Data Write Lock Bit 1 VCC 5V 5V 6.5V RST H H H PSEN L L L
(2)
ALE/ PROG
(1)
EA/ VPP 12V
P2.6 L L H
P2.7 H L H
P3.3 H L H
P3.6 H H H
P3.7 H H H
P0.7-0 Data DIN DOUT X
P3.4
P2.5-0 Address
P1.7-0
A14 A14 X
A13-8 A13-8 X
A7-0 A7-0 X
H
(2)
H/12V 12V
Write Lock Bit 2
6.5V
H
L
(2)
12V
H
H
H
L
L
X
X
X
X
Write Lock Bit 3
6.5V
H
L
12V
H
L
H
H
L
X P0.2, P0.3, P0.4 X 1EH 55H 06H
X
X
X
Read Lock Bits 1, 2, 3
5V
H
L
H
(3)
H
H
H
L
H
L
X
X
X
Chip Erase Read Atmel ID Read Device ID Read Device ID
6.5V 5V 5V 5V
H H H H
L L L L H H H
12V H H H
H L L L
L L L L
H L L L
L L L L
L L L L
X X X X
X XX 0000 XX 0001 XX 0010
X 00H 00H 00H
Notes:
1. 2. 3. 4.
Write Code Data requires a 200 ns PROG pulse. Write Lock Bits requires a 100 s PROG pulse. Chip Erase requires a 200 ns - 500 ns PROG pulse. RDY/BSY signal is output on P3.0 during programming.
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1921B-MICRO-09/02
Figure 13. Programming the Flash Memory
4.5V to 5.5V
AT89C55WD
ADDR. 0000H/4FFFH A0 - A7 A8 - A13 P1.0 - P1.7 P2.0 - P2.5 P3.4 P2.6 P2.7 P3.3 P3.6 P3.7 XTAL2 EA VIH /VPP VCC P0 PGM DATA
A14* SEE FLASH PROGRAMMING MODES TABLE
ALE
PROG
3 - 33 MHz P3.0
RDY/ BSY
XTAL1 GND
RST PSEN
VIH
Figure 14. Verifying the Flash Memory
4.5V to 5.5V
AT89C55WD
ADDR. 0000H/4FFFH A0 - A7 A8 - A13 A14* SEE FLASH PROGRAMMING MODES TABLE P2.0 - P2.5 P3.4 P2.6 P2.7 P3.3 P3.6 P3.7 XTAL 2 P1.0 - P1.7 VCC P0 PGM DATA (USE 10K PULL-UPS)
ALE VIH EA
3 - 33 MHz
XTAL1 GND
RST PSEN
VIH
Note:
*Programming address line A14 (P3.4) is not the same as the external memory address line A14 (P2.6).
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AT89C55WD
Flash Programming and Verification Characteristics
TA = 20C to 30C, VCC = 4.5V to 5.5V
Symbol VPP IPP ICC 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGH tAVQV tELQV tEHQZ tGHBL tWC Parameter Programming Supply Voltage Programming Supply Current VCC Supply Current Oscillator Frequency Address Setup to PROG Low Address Hold After PROG Data Setup to PROG Low Data Hold After PROG P2.7 (ENABLE) High to VPP VPP Setup to PROG Low VPP Hold After PROG PROG Width Address to Data Valid ENABLE Low to Data Valid Data Float After ENABLE PROG High to BUSY Low Byte Write Cycle Time 0 3 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 10 10 0.2 1 48tCLCL 48tCLCL 48tCLCL 1.0 80 s s s s s Min 11.5 Max 12.5 10 30 33 Units V mA mA MHz
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1921B-MICRO-09/02
Flash Programming and Verification Waveforms
P1.0 - P1.7 P2.0 - P2.5 P3.4 PORT 0
PROGRAMMING ADDRESS VERIFICATION ADDRESS
tAVQV
DATA IN DATA OUT
tAVGL
ALE/PROG
tDVGL
tGHDX
tGHAX tGHSL
LOGIC 1 LOGIC 0
tSHGL
VPP
tGLGH
EA/VPP
tEHSH
P2.7 (ENABLE)
tELQV tGHBL
tEHQZ
P3.0 (RDY/BSY)
BUSY
READY
tWC
Lock Bit Programming
Test Conditions Setup
Lockbit_1, 2 or 3 Data Setup
100 s ALE/PROG
VCC = 6.5V
VCC = 4.5V to 5.5V Wait 10 ms to reload new lock bit status
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AT89C55WD
Parallel Chip Erase Mode
Test Conditions Setup Test Conditions Setup
200 ns
ALE/PROG
200 ns
P3<0> VCC = 6.5V
Erase
DC Erase
Erase
DC Erase VCC = 4.5V to 5.5V Wait 10 ms before reprogramming
10 ms
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1921B-MICRO-09/02
Absolute Maximum Ratings*
Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage ............................................ 6.6V DC Output Current...................................................... 15.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics
The values shown in this table are valid for TA = -40C to 85C and VCC = 4.0V to 5.5V, unless otherwise noted.
Symbol VIL VIL1 VIH VIH1 VOL VOL1 Parameter Input Low Voltage Input Low Voltage (EA) Input High Voltage Input High Voltage Output Low Voltage Output Low Voltage
(1) (1)
Condition (Except EA)
Min -0.5 -0.5
Max 0.2 VCC -0.1 0.2 VCC -0.3 VCC+0.5 VCC+0.5 0.45 0.45
Units V V V V V V V V V V V V
(Except XTAL1, RST) (XTAL1, RST) (Ports 1,2,3) (Port 0, ALE, PSEN) IOL = 1.6 mA IOL = 3.2 mA IOH = -60 A, VCC = 5V 10%
0.2 V CC+0.9 0.7 V CC
2.4 0.75 VCC 0.9 V CC 2.4 0.75 VCC 0.9 V CC -50 -650 10 10 30 10 25 6.5 100
VOH
Output High Voltage (Ports 1,2,3, ALE, PSEN)
IOH = -25 A IOH = -10 A IOH = -800 A, V CC = 5V 10%
VOH1
Output High Voltage (Port 0 in External Bus Mode) Logical 0 Input Current (Ports 1,2,3) Logical 1 to 0 Transition Current (Ports 1,2,3) Input Leakage Current (Port 0, EA) Reset Pulldown Resistor Pin Capacitance Power Supply Current
IOH = -300 A IOH = -80 A
IIL ITL ILI RRST CIO
VIN = 0.45V VIN = 2V, VCC = 5V 10% 0.45 < VIN < V CC
A A A k pF mA mA A
Test Freq. = 1 MHz, TA = 25C Active Mode, 12 MHz
ICC Power-down Mode Notes:
(1)
Idle Mode, 12 MHz VCC = 5.5V
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2, 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power-down is 2V.
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AT89C55WD
AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF.
External Program and Data Memory Characteristics
12 MHz Oscillator Symbol 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tPXAV tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tQVWH tWHQX tRLAZ tWHLH Parameter Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulse Width PSEN Low to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN PSEN to Address Valid Address to Valid Instruction In PSEN Low to Address Float RD Pulse Width WR Pulse Width RD Low to Valid Data In Data Hold After RD Data Float After RD ALE Low to Valid Data In Address to Valid Data In ALE Low to RD or WR Low Address to RD or WR Low Data Valid to WR Transition Data Valid to WR High Data Hold After WR RD Low to Address Float RD or WR High to ALE High 43 200 203 23 433 33 0 123 tCLCL-25 0 97 517 585 300 3tCLCL-50 4tCLCL-75 tCLCL-30 7tCLCL-130 tCLCL-25 0 tCLCL+25 400 400 252 0 2tCLCL-28 8tCLCL-150 9tCLCL-165 3tCLCL+50 75 312 10 6tCLCL-100 6tCLCL-100 5tCLCL-90 0 59 tCLCL-8 5tCLCL-80 10 43 205 145 0 tCLCL-25 127 43 48 233 tCLCL-25 3tCLCL-45 3tCLCL-60 Min Max Variable Oscillator Min 0 2tCLCL-40 tCLCL-25 tCLCL-25 4tCLCL-65 Max 33 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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1921B-MICRO-09/02
External Program Memory Read Cycle
tLHLL ALE tAVLL PSEN tPLAZ tLLAX PORT 0
A0 - A7
tLLPL
tLLIV tPLIV
tPLPH
tPXAV tPXIZ tPXIX
INSTR IN A0 - A7
tAVIV PORT 2
A8 - A15 A8 - A15
External Data Memory Read Cycle
tLHLL ALE tWHLH PSEN tLLDV tLLWL RD tAVLL PORT 0 tLLAX tRLAZ
DATA IN
tRLRH
tRLDV
tRHDZ tRHDX
A0 - A7 FROM PCL INSTR IN
A0 - A7 FROM RI OR DPL
tAVWL tAVDV PORT 2
P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH
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1921B-MICRO-09/02
AT89C55WD
External Data Memory Write Cycle
tLHLL ALE tWHLH PSEN tLLWL WR tAVLL PORT 0 tLLAX tQVWX tWLWH
tQVWH
DATA OUT
tWHQX
A0 - A7 FROM PCL INSTR IN
A0 - A7 FROM RI OR DPL
tAVWL PORT 2
P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH
External Clock Drive Waveforms
tCHCX
VCC - 0.5V 0.7 VCC 0.2 VCC - 0.1V 0.45V
tCHCX tCLCH tCHCL
tCLCX tCLCL
External Clock Drive
Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall Time Min 0 30 12 12 5 5 Max 33 Units MHz ns ns ns ns ns
31
1921B-MICRO-09/02
Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for VCC = 4.0V to 5.5V and Load Capacitance = 80 pF.
12 MHz Osc Symbol tXLXL tQVXH tXHQX tXHDX tXHDV Parameter Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold After Clock Rising Edge Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data Valid Min 1.0 700 50 0 700 Max Variable Oscillator Min 12tCLCL 10tCLCL-133 2tCLCL-80 0 10tCLCL-133 Max Units s ns ns ns ns
Shift Register Mode Timing Waveforms
INSTRUCTION ALE CLOCK 0 1 2 3 4 5 6 7 8
tXLXL tQVXH
WRITE TO SBUF
tXHQX
0 1 2 3 4 5 6 7 SET TI
VALID VALID VALID VALID VALID
OUTPUT DATA CLEAR RI INPUT DATA
tXHDV
VALID VALID
tXHDX
VALID
SET RI
AC Testing Input/Output Waveforms(1)
VCC - 0.5V 0.2 VCC + 0.9V TEST POINTS 0.45V 0.2 VCC - 0.1V
Note:
1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0.
Float Waveforms(1)
V LOAD+ V LOAD V LOAD Note:
0.1V 0.1V
V OL Timing Reference Points V OL +
0.1V
0.1V
1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs.
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AT89C55WD
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AT89C55WD
Ordering Information
Speed (MHz) 24 Power Supply 4.0V to 5.5V Ordering Code AT89C55WD-24AC AT89C55WD-24JC AT89C55WD-24PC AT89C55WD-24AI AT89C55WD-24JI AT89C55WD-24PI 33 4.5V to 5.5V AT89C55WD-33AC AT89C55WD-33JC AT89C55WD-33PC Package 44A 44J 40P6 44A 44J 40P6 44A 44J 40P6 Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C)
Package Type 44A 44J 40P6 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44-lead, Plastic J-leaded Chip Carrier (PLCC) 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP)
33
1921B-MICRO-09/02
Package Information
44A - TQFP
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 11.75 9.90 11.75 9.90 0.30 0.09 0.45 NOM - - 1.00 12.00 10.00 12.00 10.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 12.25 10.10 12.25 10.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 44A REV. B
R
34
AT89C55WD
1921B-MICRO-09/02
AT89C55WD
44J - PLCC
1.14(0.045) X 45
PIN NO. 1 IDENTIFIER
1.14(0.045) X 45 0.318(0.0125) 0.191(0.0075)
E1 B
E
B1
D2/E2
e D1 D A A2 A1
0.51(0.020)MAX 45 MAX (3X)
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E1 D2/E2 B B1 e MIN 4.191 2.286 0.508 17.399 16.510 17.399 16.510 14.986 0.660 0.330 NOM - - - - - - - - - - 1.270 TYP MAX 4.572 3.048 - 17.653 16.662 17.653 16.662 16.002 0.813 0.533 Note 2 Note 2 NOTE
10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 44J REV. B
R
35
1921B-MICRO-09/02
40P6 - PDIP
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
A1
C eB
0 ~ 15
REF
SYMBOL A A1 D E E1 B
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 52.070 15.240 13.462 0.356 1.041 3.048 0.203 15.494 NOM - - - - - - - - - - 2.540 TYP MAX 4.826 - 52.578 15.875 13.970 0.559 1.651 3.556 0.381 17.526 Note 2 Note 2 NOTE
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
B1 L C eB e
09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 40P6 REV. B
R
36
AT89C55WD
1921B-MICRO-09/02
Atmel Headquarters
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e-mail
literature@atmel.com
Web Site
http://www.atmel.com
(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
ATMEL (R) is a registered trademark of Atmel. MCS (R)-51 is a registered trademark of Intel Corporation. Other terms and product names may be the trademarks of others.
Printed on recycled paper.
1921B-MICRO-09/02 xM

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