| PART |
Description |
Maker |
| XCR5128C DS042 |
with Enhanced Clocking
From old datasheet system
|
Xilinx
|
| XCR3064A-10CP56C XCR3064A-10PC44C XCR3064A-10VQ100 |
64 Macrocell CPLD With Enhanced Clocking
|
Xilinx, Inc
|
| XCR5128C-12VQ100C XCR5128C-12VQ100I XCR5128C-15VQ1 |
128 Macrocell CPLD with Enhanced Clocking
|
XILINX[Xilinx, Inc]
|
| XCR5064C-1 XCR5064C-10PC44I XCR5064C-10VQ44I XCR50 |
64 Macrocell CPLD with Enhanced Clocking EE PLD, 12 ns, PQCC44
|
Xilinx, Inc.
XILINX[Xilinx, Inc]
|
| AN-823 |
Direct Digital Synthesizers in Clocking Applications Time
|
Analog Devices
|
| XCR3032C DS040 XCR3032C-12VQ44C |
EE PLD, 12 ns, PQFP44
32 Macrocell CPLD with Enhanced Clocking(带增强时钟控制的32宏单元复杂可编程逻辑器件) 32宏单元CPLD增强型时钟（带增强时钟控制的32个宏单元复杂可编程逻辑器件
From old datasheet system
|
XILINX INC
Xilinx, Inc.
|
| CS2000P-CZZR |
Clocking-Timing IC General Purpose PLL Crystal PHASE LOCKED LOOP, 30 MHz, PDSO10
|
Cirrus Logic, Inc.
|
| CS2100P-CZZR |
Clocking-Timing IC General Purpose PLL Crystal PHASE LOCKED LOOP, 30 MHz, PDSO10
|
Cirrus Logic, Inc.
|
| CS230001-CZZR |
Clocking-Timing IC Clock BW1Hz w/ 1x 2x 4x 8x PLL BASED CLOCK DRIVER, PDSO10
|
Cirrus Logic, Inc.
|
| ICS9248-98 ICS9248YF-98LF-T |
150 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 0.300 INCH, LEAD FREE, MO-118, SSOP-48
Single Chip, ALI 1631 Chipset with up to 166MHz and Over Clocking
|
Integrated Device Technology, Inc.
ICS
|
| ELJND102KF ELJND102DF ELJNA221JF ELJFC220DF ELJFC2 |
If you are looking for a Chinese version of this datasheet, more; Vcc (V): 3 V to 5.25 V; Package: QFN;
If you are looking for a Chinese version of this datasheet, more; Vcc (V): 2.4 V to 5.25 V; Package: TQFP;
TAXI(TM) Compatible HOTLink(R) Transceiver; Features: 8-bit 4B/5B or 10-bit 5B/6B,BIST; Frequency Range: 50 to 200 Mbps; Standard: TAXIchip;
EZ-USB HX2LP(TM) Low-Power USB 2.0 Hub Controller Family; Development Kit: CY4606; Hub Ports: 4; USB Application: High Speed Hub;
Independent Clock Quad HOTLink II(TM) Reclocking Deserializer; Features: Quad Channel Deserializer; Package: BGA; Pins/Ball: 256; Standard
Independent Clock HOTLink II(TM) Serializer and Reclocking Deserializer; Features: Single Channel SERDES; Package: BGA; Pins/Ball: 256
EZ-USB AT2LP(TM) USB 2.0 to ATA/ATAPI Bridge; # Endpoints: 7; Core: N/A; Data Transfers: Bulk, Interrupt, Isochronous; Development Kit: CY4615B
Independent Clock HOTLink II(TM) Dual Serializer and Dual Reclocking Deserializer; Features: Dual Channel SERDES; Package: BGA; Pins/Ball: 256; Standard: SMPTE|DVB-ASI
Independent Clock Quad HOTLink II™ Transceiver; Features: Independent Clocking, 8B/10B, Redundancy, BIST, JTAG; Frequency Range: 0.2 to 1.5 Gbps; Standard: Ethernet, Fibre Channel, ESCON, DVB-ASI;
Single-channel HOTLink II(TM) Transceiver; Features: 8B/10B, Redundancy, BIST, JTAG; Frequency Range: 0.2 to 1.5 Gbps; Standard: Ethernet, Fibre Channel, ESCON, DVB-ASI;
Dual-channel HOTLink II(TM) Transceiver; Features: Channel Bonding, 8B/10B, Redundancy, BIST, JTAG; Frequency Range: 0.2 to 1.5 Gbps; Standard: Ethernet, Fibre Channel, ESCON, DVB-ASI;
EZ-Host(TM) Programmable Embedded USB Host and Peripheral Controller with Automotive AEC Grade Support; Memory Architecture: ROM/RAM; Memory Size: 16 KB; Package: TQFP; # Endpoints: 8
EZ-USB SX2(TM) High Speed USB Interface Device; # Endpoints: 7; Core: N/A; Data Transfers: Bulk, Interrupt, Isochronous; Development Kit: CY3683
STAR-250/CYIS1SM0250AA; Application: Satellite Optical Altitude, Comm Sensors, Spacecraft Visual Monitors, Nuclear; Features: Rolling Shutter, Windowing, On-Chip FPN Correction, Double Slope; Frame Rate: 29 fps; Optical Format: 1 inch
Programmable System on a Chip; Voltage: 4.75V - 5.25V; GPIO: 24; Analog Blocks: 12; Digital Blocks: 16; Flash: 32KB; RAM: 2KB; Temp: E; Comm: I2C, SPI, UART; Package: 28 SSOP
If you are looking for a Chinese version of this datasheet, more; Vcc (V): 2.4 V to 5.25 V; Package: TQFP; 片式电感
If you are looking for a Chinese version of this datasheet, more; Vcc (V): 3 V to 5.25 V; Package: QFN; 片式电感
Chip inductors 片式电感
64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs; Density: 64 Kb; Organization: 4Kb x 18; VCC(V): 3.0 to 3.6 V; Speed: 40 MHz 片式电感
Independent Clock Quad HOTLink II(TM) Reclocking Deserializer; Features: Quad Channel Deserializer; Package: BGA; Pins/Ball: 256; Standard: SMPTE|DVB-ASI 片式电感
EZ-USB AT2LP(TM) USB 2.0 to ATA/ATAPI Bridge; # Endpoints: 7; Core: N/A; Data Transfers: Bulk, Interrupt, Isochronous; Development Kit: CY4615B 片式电感
enCoRe(TM) USB Combination Low-Speed USB and PS/2 Peripheral Controller; # Endpoints: 3; #of I/O: 10; Core: M8B (8-bit RISC); Development Kit: CY3654, CY3654-P05 1 ELEMENT, 22 uH, FERRITE-CORE, GENERAL PURPOSE INDUCTOR, SMD
Chip inductors 1 ELEMENT, 0.22 uH, NON-MAGNETIC-CORE, GENERAL PURPOSE INDUCTOR, SMD
1.3 MPxl Rolling Shutter CMOS Image Sensor; Application: Machine Vision, Instrumentation, Microscopy; Features: Rolling Shutter, Windowing, On-Chip FPN Correction, Double Slope; Frame Rate: 7 fps; Optical Format: 2/3 inch
|
Panasonic Corporation
Panasonic, Corp.
|
|
