| PART |
Description |
Maker |
| W9725G6KB25A W9725G6KB-25 W9725G6KB-18 W9725G6KB-3 |
DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask
|
Winbond
|
| MC74HC354DW MC54_74HC354 ON1412 MC54HC354 MC74HC35 |
8-Input Data Selector/Multiplexer With Data and Address Latches and 3-State Outputs
8-INPUT DATA SELECTOR/MULTLPLEXER WLTH DATA AND ADDRESS LATCHER AND 3-STATE OUTPUTS
From old datasheet system
|
Motorola, Inc.
ON Semi
MOTOROLA[Motorola, Inc]
|
| HI-8787 HI-8787PQI HI-8787PQT HI-8788 HI-8788PQI H |
16 Bit Parallel data converted to 429 and 561 serial data out
ARINC INTERFACE DEVICE 16-BIT PARALLEL DATA CONVERTED 429&561 SERIAL DATA OUT
512 MACROCELL 3.3 VOLT ZERO POWER ISP CP - NOT RECOMMENDED for NEW DESIGN
|
HOLTIC[Holt Integrated Circuits]
|
| W9751G6KB-18 W9751G6KB-25 W9751G6KB-3 W9751G6KB25A |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| R2705E |
27.195MHz FSK Radio Data Receiver for Manchester Data Format
|
List of Unclassifed Manufacturers
|
| K4D26323RA K4D26323RA-GC2A K4D26323RA-GC33 K4D2632 |
1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL
|
SAMSUNG SEMICONDUCTOR CO. LTD.
SAMSUNG[Samsung semiconductor]
Samsung Electronic
|
| W9412G6JH W9412G6JH-5 |
2M ?4 BANKS ?16 BITS DDR SDRAM
Double Data Rate architecture; two data transfers per clock cycle
|
Winbond
|
| W972GG6JB W972GG6JB-25 |
16M ?8 BANKS ?16 BIT DDR2 SDRAM
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| S5T0167X01 |
DTMF DIALER FOR BINARY DATA-IN Data Sheet
|
Samsung Electronic
|
| ST7FDALI ST7FDALIF2B6 ST7FDALIF2M6 ST7FLITE2 ST7FL |
8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI, DALI (DATA BRIEFING)
|
ST Microelectronics
|
| W9412G2IB W9412G2IB4 W9412G2IB-6I |
1M × 4 BANKS × 32 BITS GDDR SDRAM
Double Data Rate architecture; two data transfers per clock cycle
4M X 32 DDR DRAM, 0.7 ns, PBGA144
|
Winbond
WINBOND ELECTRONICS CORP
|
