| PART |
Description |
Maker |
| AS7C33512PFD18A-133TQCN AS7C33512PFD18A-133TQIN AS |
3.3V 512K x 18 pipeline burst synchronous SRAM 512K X 18 STANDARD SRAM, 4.5 ns, PQFP100
3.3V 512K x 18 pipeline burst synchronous SRAM 512K X 18 STANDARD SRAM, 4 ns, PQFP100
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Alliance Semiconductor, Corp.
Alliance Semiconductor Corp...
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| IS61NVP25636A-200TQI IS61NLP25636A-200B2I IS61NLP2 |
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 256K X 36 ZBT SRAM, 3.1 ns, PQFP100
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 256K X 36 ZBT SRAM, 3.1 ns, PBGA119
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 256K X 36 ZBT SRAM, 2.6 ns, PQFP100
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 256K X 36 ZBT SRAM, 2.6 ns, PBGA119
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 512K X 18 ZBT SRAM, 3.1 ns, PBGA165
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 512K X 18 ZBT SRAM, 2.6 ns, PBGA165
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 512K X 18 ZBT SRAM, 2.6 ns, PBGA119
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 512K X 18 ZBT SRAM, 3.1 ns, PBGA119
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 512K X 18 ZBT SRAM, 2.6 ns, PQFP100
256K x 36 and 512K x 18 9Mb, PIPELINE (NO WAIT) STATE BUS SRAM 512K X 18 ZBT SRAM, 3.1 ns, PQFP100
256K X 36 ZBT SRAM, 3.1 ns, PBGA165
|
Integrated Silicon Solution, Inc.
INTEGRATED SILICON SOLUTION INC
|
| WEDPZ512K72S-150BC WEDPZ512K72S-150BI WEDPZ512K72S |
512K x 72 SYNCHRONOUS PIPELINE BURST ZBL SRAM
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WEDC[White Electronic Designs Corporation]
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| WED2ZLRSP01S42BC WED2ZLRSP01S50BI WED2ZLRSP01S38BC |
512K x 32/256K x 32 Dual Array Synchronous Pipeline Burst NBL SRAM
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WEDC[White Electronic Designs Corporation]
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| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
| AS7C3256PFD18A-4TQC AS7C3256PFD16A-4TQC AS7C3256PF |
3.3V 256K x 16 pipeline burst synchronous SRAM, 150 MHz
3.3V 256K x 16 pipeline burst synchronous SRAM, 100 MHz
256K X 18 STANDARD SRAM, 4 ns, PQFP100 14 X 20 MM, TQFP-100
256K X 16 STANDARD SRAM, 4 ns, PQFP100 14 X 20 MM, TQFP-100
3.3V 256K x 16/18 pipeline burst synchronous SRAM
3.3V 256K x 18 pipeline burst synchronous SRAM, 166 MHz
3.3V 256K x 18 pipeline burst synchronous SRAM, 150 MHz
3.3V 256K x 18 pipeline burst synchronous SRAM, 133 MHz
3.3V 256K x 18 pipeline burst synchronous SRAM, 100 MHz
3.3V 256K x 16 pipeline burst synchronous SRAM, 133 MHz
3.3V 256K x 16 pipeline burst synchronous SRAM, 166MHz
|
Alliance Semiconductor, Corp.
|
| EUA6210 EUA6210MIR1 |
128K x 36, 3.3V, Sync Burst Pipeline
Output Capacitor-less 67mW Stereo Headphone Amplifier
128K x 32, 3.3V, Sync Burst Pipeline
|
寰蜂俊绉???′唤??????
Eutech Microelectronics Inc
德信科技股份有限公司
|
| CY7C1372CV25-167AI CY7C1372CV25-167BGI CY7C1372CV2 |
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 3 ns, PQFP100
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 3 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 3 ns, PBGA119
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 2.8 ns, PBGA119
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 1M X 18 ZBT SRAM, 2.8 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 512K X 36 ZBT SRAM, 3 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 512K X 36 ZBT SRAM, 3 ns, PQFP100
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 512K X 36 ZBT SRAM, 3.4 ns, PQFP100
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 512K X 36 ZBT SRAM, 3.4 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM with NoBLArchitecture 12k × 36/1M × 18流水线的SRAM架构的总线延迟
CAP,Ceramic,10000pF,500VDC,10-% Tol,10% Tol,X7R-TC Code,-15,15%-TC,30ppm-TC RoHS Compliant: Yes
512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
|
Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
|
| AS7C33256PFS32A AS7C33256PFS36A AS7C33256PFS32A-16 |
3.3V 256K x 32/36 pipeline burst synchronous SRAM
3.3V 256K x 32 pipeline burst synchronous SRAM, clock speed - 166 MHz
|
Alliance Semiconductor
|
| AS7C33256PFD16A AS7C33256PFD18A AS7C33256PFD18A-10 |
3.3V 256K x 16/18 pipeline burst synchronous SRAM
3.3V 256K x 18 pipeline burst synchronous SRAM, clock speed - 100 MHz
3.3V 256K x 18 pipeline burst synchronous SRAM, clock speed - 133 MHz
3.3V 256K x 18 pipeline burst synchronous SRAM, clock speed - 150 MHz
3.3V 256K x 18 pipeline burst synchronous SRAM, clock speed - 166 MHz
3.3V 256K x 16 pipeline burst synchronous SRAM, clock speed - 133 MHz
3.3V 256K x 16 pipeline burst synchronous SRAM, clock speed - 100 MHz
3.3V 256K x 16 pipeline burst synchronous SRAM, clock speed - 150 MHz
3.3V 256K x 16 pipeline burst synchronous SRAM, clock speed - 166 MHz
|
Alliance Semiconductor
|
| CY7C1049CV33 CY7C1049CV33-15ZXC CY7C1049CV33-10VC |
4-Mbit (512K x 8) Static RAM
512K x 8 Static RAM 512K X 8 STANDARD SRAM, 15 ns, PDSO36
512K x 8 Static RAM 512K X 8 STANDARD SRAM, 15 ns, PDSO44
512K x 8 Static RAM 12k × 8静态RAM
512K x 8 Static RAM 512K X 8 STANDARD SRAM, 12 ns, PDSO44
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CYPRESS[Cypress Semiconductor]
Cypress Semiconductor, Corp.
Cypress Semiconductor Corp.
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