| PART |
Description |
Maker |
| M13S2561616A-2S |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| M14D5121632A-2K |
Internal pipelined double-data-rate architecture; two data access per clock cycle
|
Elite Semiconductor Mem...
|
| MAX9320A MAX9320 MAX9320EUAT |
1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers LOW SKEW CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
1:2 Differential LVPECL/ LVECL/HSTL Clock and Data Drivers
|
Maxim Integrated Products, Inc.
MAXIM - Dallas Semiconductor
|
| SY87701V SY87701VHC SY87701VZC |
5V/3.3V 32-1250Mbps AnyRateCLOCK AND DATA RECOVERY
5V/3.3V 32-1250Mbps AnyRate CLOCK AND DATA RECOVERY
5V/3.3V 32-1250Mbps AnyRate⑩ CLOCK AND DATA RECOVERY
|
Micrel Semiconductor,Inc.
MICREL[Micrel Semiconductor]
|
| W9412G2IB W9412G2IB4 W9412G2IB-6I |
1M × 4 BANKS × 32 BITS GDDR SDRAM
Double Data Rate architecture; two data transfers per clock cycle
4M X 32 DDR DRAM, 0.7 ns, PBGA144
|
Winbond
WINBOND ELECTRONICS CORP
|
| MAX9316A MAX9316AEWP |
1:5 Differential LVPECL/LVECL/ HSTL Clock and Data Driver
1:5 Differential (LV)PECL/(LV)ECL/HSTL Clock and Data Driver
|
MAXIM - Dallas Semiconductor
MAXIM[Maxim Integrated Products]
|
| NBSG53AMNG NBSG53AMNR2G NBSG53A_06 NBSG53ABA NBSG5 |
2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip−Flop/Clock Divider with Reset and OLS
|
ONSEMI[ON Semiconductor]
|
| TSM600-250 |
The SY87702L is a complete Clock Recovery and Data
retiming integrated circuit for data rates from 28Mbps up to
2.5Gbps NRZ.
PolySwitch PTC Devices Overcurrent Protection Device
|
MACOM
Tyco Electronics
|
| SY100EL15LZG-TR |
Clock and Timing - Clock and Data Distribution
|
Microchip
|
| SY100EP15VK4G-TR |
Clock and Timing - Clock and Data Distribution
|
Microchip
|
| SY100EPT21LKG SY100EPT21LKG-TR SY100EPT21LZG |
Clock and Timing - Clock and Data Distribution
|
Microchip
|
