| PART |
Description |
Maker |
| CY7C1305AV25 CY7C1305AV25-133BZC CY7C1305AV25-167 |
18-Mbit Burst of 4 Pipelined SRAM with QD(TM) Architecture
18-MBIT BURST OF 4 PIPELINED SRAM WITH QDR ARCHITECTURE
|
CYPRESS[Cypress Semiconductor]
|
| CY7C1303BV2512 CY7C1303BV25-167BZC |
18-Mbit Burst of Two-Pipelined SRAM with QDR? Architecture
|
Cypress Semiconductor
|
| CY7C1304DV25-100BZXC |
9-Mbit Burst of 4 Pipelined SRAM with QDR(TM) Architecture
|
Cypress
|
| CY7C1302DV25 CY7C1302DV25-167 CY7C1302DV25-100 CY7 |
9-Mbit Burst of Two Pipelined SRAMs with QDR(TM) Architecture
9-Mbit Burst of Two Pipelined SRAMs with QDR Architecture
|
CYPRESS[Cypress Semiconductor]
|
| CY7C1303CV25-167BZC CY7C1306CV25-167BZC CY7C1306CV |
18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture
|
Cypress Semiconductor
|
| CY7C1307BV25-167BZC |
18-Mbit Burst of 4 Pipelined SRAM with QDR⑩ Architecture
|
Cypress Semiconductor
|
| CY7C1303AV25-100BZC CY7C1306AV25-100BZC CY7C1303AV |
Memory : Sync SRAMs
18-Mb Burst of 2 Pipelined SRAM with QDR(TM) Architecture
18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Architecture
18-Mb Burst of 2 Pipelined SRAM with QDR Architecture
18-Mb Burst of 2 Pipelined SRAM with QDR?/a> Architecture
|
Cypress Semiconductor
|
| BBF2805SE BBF2815S BBF2812S BBF2805SK BBF2803SH BB |
3.3V, 20W DC-DC converter
15V, 20W DC-DC converter
12V, 20W DC-DC converter
Analog IC
18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL™ Architecture
9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL™ Architecture
18-Mbit QDR™-II SRAM 2-Word Burst Architecture
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture
20W DC-DC Converter(输出功率20WDC-DC转换
|
M.S. Kennedy Corp.
M.S. Kennedy Corporation
|
| M36P0R8070E0 M36P0R8070E0ZACE M36P0R8070E0ZACF |
256 Mbit (x16, multiple bank, multilevel, burst) Flash memory 128 Mbit (burst) PSRAM, 1.8 V supply, multichip package
|
Numonyx B.V
|
| CAT64LC10ZJ CAT64LC10ZP CAT64LC10J-TE7 CAT64LC10J- |
18-Mbit QDR™-II SRAM 4-Word Burst Architecture
18-Mbit DDR-II SRAM 2-Word Burst Architecture
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
4-Mbit (256K x 18) Flow-Through Sync SRAM SPI串行EEPROM
SPI Serial EEPROM SPI串行EEPROM
|
Analog Devices, Inc.
|
| M36P0R9060E0 M36P0R9060E0ZACE M36P0R9060E0ZACF |
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash memory 64 Mbit (Burst) PSRAM, 1.8V supply, Multi-Chip Package
|
STMicroelectronics
|
| CY7C1472BV25-167BZXC CY7C1472BV25-167BZXI CY7C1472 |
2M X 36 ZBT SRAM, 3 ns, PBGA165
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL垄芒 Architecture
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL?/a> Architecture
|
CYPRESS SEMICONDUCTOR CORP
|
