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CY7C1261V18 - 36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit QDR垄芒-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

CY7C1261V18_4154153.PDF Datasheet

Part No.

CY7C1261V18 CY7C1261V18-300BZC CY7C1261V18-300BZI CY7C1261V18-300BZXC CY7C1261V18-300BZXI CY7C1261V18-333BZC CY7C1261V18-333BZI CY7C1261V18-333BZXC CY7C1261V18-333BZXI CY7C1261V18-375BZC CY7C1261V18-375BZI CY7C1261V18-375BZXC CY7C1261V18-375BZXI CY7C1261V18-400BZC CY7C1261V18-400BZI CY7C1261V18-400BZXC CY7C1261V18-400BZXI CY7C1263V18 CY7C1263V18-300BZC CY7C1263V18-300BZI CY7C1263V18-300BZXC CY7C1263V18-300BZXI CY7C1263V18-333BZC CY7C1263V18-333BZI CY7C1263V18-333BZXC CY7C1263V18-333BZXI CY7C1263V18-375BZC CY7C1263V18-375BZI CY7C1263V18-375BZXC CY7C1263V18-375BZXI CY7C1276V18

Description

36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
36-Mbit QDR垄芒-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

File Size

1,096.09K / 28 Page

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Cypress Semiconductor

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Full text search : 36-Mbit QDR⑩-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit QDR垄芒-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

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CY7C1310CV18-167BZXC CY7C1314CV18-167BZI CY7C1314C	18-Mbit QDR-IISRAM 2-Word Burst Architecture 2M X 8 QDR SRAM, 0.5 ns, PBGA165 18-Mbit QDR-IISRAM 2-Word Burst Architecture 512K X 36 QDR SRAM, 0.5 ns, PBGA165	Cypress Semiconductor, Corp.
Y5-12-12 Y5-12-15 Y5-12-5 Y5-12S15 Y5-12S5	72-Mbit QDR-II™ SRAM 2-Word Burst Architecture 256K (32K x 8) Static RAM 16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs 模拟IC 72-Mbit QDR-II SRAM 2-Word Burst Architecture USB LOW SPEED, 3 ENDPOINT, ENCORE II, 16-SOIC	东电?中国)投资有限公司
M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823	18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V 36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V 18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; 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