| PART |
Description |
Maker |
| IS61LPD51218T/D IS61LPD25632T/D IS61SPD25632T/D IS |
256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, DOUBLE-CYCLE DESELECT STATIC RAM 256K × 3256K × 3612K采样× 18 SYNCHRONOU?管道，双循环取消选择静态RAM
256K X 36 CACHE SRAM, 3.5 ns, PQFP100 TQFP-100
256K x 32/ 256K x 36/ 512K x 18 SYNCHRONOUS PIPELINE/ DOUBLE-CYCLE DESELECT STATIC RAM
|
Integrated Silicon Solution, Inc.
Integrated Silicon Solution Inc
|
| IS61NVP51236-200B3 IS61NLP51236-250B3 IS61NVP51236 |
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM 512K X 36 ZBT SRAM, 3.1 ns, PBGA165
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM 512K X 36 ZBT SRAM, 2.6 ns, PBGA165
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM 512K X 36 ZBT SRAM, 2.6 ns, PQFP100
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM 1M X 18 ZBT SRAM, 2.6 ns, PQFP100
|
Integrated Silicon Solution, Inc.
INTEGRATED SILICON SOLUTION INC
|
| IS61NVVP51236-200BI IS61NVVP51236-250B IS61NVVP512 |
256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM 512K X 36 ZBT SRAM, 3 ns, PBGA119
256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM 512K X 36 ZBT SRAM, 2.6 ns, PBGA119
|
Integrated Silicon Solution, Inc.
|
| AS7C33512PFD18A-133TQCN AS7C33512PFD18A-133TQIN AS |
3.3V 512K x 18 pipeline burst synchronous SRAM 512K X 18 STANDARD SRAM, 4.5 ns, PQFP100
3.3V 512K x 18 pipeline burst synchronous SRAM 512K X 18 STANDARD SRAM, 4 ns, PQFP100
|
Alliance Semiconductor, Corp.
Alliance Semiconductor Corp...
|
| WED2ZL64512S WED2ZL64512S35BC WED2ZL64512S38BC WED |
512K x 64 Synchronous Pipeline NBL SRAM
|
White Electronic Designs Corporation
|
| IS61SPS51218T-133TQI IS61SPS51218T-150TQ IS61SPS51 |
512K X 18 CACHE SRAM, 3.8 ns, PBGA119
512K x 18 synchronous pipeline, single-cycle deselect static RAM
256K x 32 synchronous pipeline, single-cycle deselect static RAM
256K x 36 synchronous pipeline, single-cycle deselect static RAM
256K X 36 CACHE SRAM, 4 ns, PQFP100
512K X 18 CACHE SRAM, 4 ns, PQFP100
|
Integrated Silicon Solution Inc
|
| IS61NVP51236 IS61NVP51236-200B3 IS61NVP51236-200B3 |
256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM
|
ISSI[Integrated Silicon Solution, Inc]
|
| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
| AM29LV800DB-70EF AM29LV800DB-90EF AM29LV800DB-70WC |
Flash Memory IC; Memory Size:8Mbit; Package/Case:48-TSOP; Supply Voltage Max:3V; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes; Access Time, Tacc:70nS; Series:AM29 RoHS Compliant: Yes 512K X 16 FLASH 3V PROM, 70 ns, PDSO48
512K X 16 FLASH 3V PROM, 90 ns, PDSO48
512K X 16 FLASH 3V PROM, 70 ns, PBGA48
512K X 16 FLASH 3V PROM, 90 ns, PBGA48
512K X 16 FLASH 3V PROM, 120 ns, PDSO48
512K X 16 FLASH 3V PROM, 120 ns, PDSO44
512K X 16 FLASH 3V PROM, 90 ns, PDSO44
|
Spansion, Inc.
SPANSION LLC
|
| TDC1011B2A TDC1011B2C TDC1011C3C TDC1011B7C TDC101 |
8-BIT, DSP-PIPELINE REGISTER, CDIP24
8-BIT, DSP-PIPELINE REGISTER, CQCC28
|
TRW INC
|
| CY7C1382CV25-167AI CY7C1382CV25-200BZI CY7C1382CV2 |
512K x 36 pipelined SRAM, 167MHz
512K x 36/1M x 18 Pipelined SRAM 512K X 36 CACHE SRAM, 3 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM 1M X 18 CACHE SRAM, 3.4 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM 1M X 18 CACHE SRAM, 2.8 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM 1M X 18 CACHE SRAM, 2.8 ns, PQFP100
512K x 36/1M x 18 Pipelined SRAM 1M X 18 CACHE SRAM, 2.6 ns, PBGA119
512K x 36/1M x 18 Pipelined SRAM 1M X 18 CACHE SRAM, 3 ns, PBGA119
512K x 36/1M x 18 Pipelined SRAM 1M X 18 CACHE SRAM, 2.6 ns, PBGA165
512K x 36/1M x 18 Pipelined SRAM 1M X 18 CACHE SRAM, 3 ns, PQFP100
512K x 36/1M x 18 Pipelined SRAM 1M X 18 CACHE SRAM, 2.6 ns, PQFP100
512K x 36/1M x 18 Pipelined SRAM 1M X 18 CACHE SRAM, 3 ns, PBGA165
TRANS DARL PNP 100V 8A TO-220FP 1M X 18 CACHE SRAM, 3.4 ns, PQFP100
512K x 36 pipelined SRAM, 225MHz
|
Cypress Semiconductor, Corp.
|
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