| PART |
Description |
Maker |
| M5LV-512/256-10SAI M5LV-512/256-12SAC M5LV-256/160 |
EE PLD, 10 ns, PBGA352 BGA-352
EE PLD, 12 ns, PBGA352 BGA-352
Fifth Generation MACH Architecture EE PLD, 10 ns, PQFP208
Fifth Generation MACH Architecture EE PLD, 12 ns, PQFP208
Fifth Generation MACH Architecture EE PLD, 20 ns, PQFP160
Fifth Generation MACH Architecture EE PLD, 5.5 ns, PQFP100
Fifth Generation MACH Architecture EE PLD, 15 ns, PQFP160
Fifth Generation MACH Architecture EE PLD, 10 ns, PQFP160
EE PLD, 15 ns, PBGA352 BGA-352
Fifth Generation MACH Architecture EE PLD, 5.5 ns, PQFP144
EE PLD, 15 ns, PQFP160 PLASTIC, QFP-160
CONNECTOR ACCESSORY EE PLD, 5.5 ns, PQFP100
Fifth Generation MACH Architecture EE PLD, 15 ns, PQFP208
Fifth Generation MACH Architecture EE PLD, 7.5 ns, PQFP208
Fifth Generation MACH Architecture EE PLD, 10 ns, PQFP100
EE PLD, 15 ns, PQFP100 TQFP-100
Fifth Generation MACH Architecture EE PLD, 20 ns, PQFP208
EE PLD, 12 ns, PQFP100 TQFP-100
EE PLD, 12 ns, PBGA256 BGA-256
|
Lattice Semiconductor, Corp.
LATTICE SEMICONDUCTOR CORP
|
| CY7C1303AV25-100BZC CY7C1306AV25-100BZC CY7C1303AV |
Memory : Sync SRAMs
18-Mb Burst of 2 Pipelined SRAM with QDR(TM) Architecture
18-Mb Burst of 2 Pipelined SRAM with QDR⑩ Architecture
18-Mb Burst of 2 Pipelined SRAM with QDR Architecture
18-Mb Burst of 2 Pipelined SRAM with QDR?/a> Architecture
|
Cypress Semiconductor
|
| EP2SGX60C EP2SGX30CF780C5N EP2SGX30D EP2SGX60CF780 |
Section I. Stratix II GX Device Data Sheet
Support for numerous single-ended and differential I/O standards
Section I. Stratix II GX Device Data Sheet
|
Altera Corporation
|
| CAT64LC10ZJ CAT64LC10ZP CAT64LC10J-TE7 CAT64LC10J- |
18-Mbit QDR™-II SRAM 4-Word Burst Architecture
18-Mbit DDR-II SRAM 2-Word Burst Architecture
36-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)
4-Mbit (256K x 18) Flow-Through Sync SRAM SPI串行EEPROM
SPI Serial EEPROM SPI串行EEPROM
|
Analog Devices, Inc.
|
| CY7C1515KV18-250BZXI CY7C1515KV18-300BZC CY7C1515K |
72-Mbit QDR II SRAM 4-Word Burst Architecture
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 QDR SRAM, 0.45 ns, PBGA165
|
http://
Cypress Semiconductor, Corp.
|
| CY7C1568KV18-550BZXC |
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 4M X 18 DDR SRAM, 0.45 ns, PBGA165
|
Cypress Semiconductor, Corp.
|
| DA0620 |
Attenuator 5 Section
|
DAICO[DAICO Industries, Inc.]
|
| DA0984-1 |
GaAs 4 Section Attenuator
|
DAICO[DAICO Industries, Inc.]
|
|
