| PART |
Description |
Maker |
| TSOP7000 |
IR Receiver for High Data Rate PCM at 455 kHz
|
Vishay
|
| TSOP7000SW1 |
IR Receiver for High Data Rate PCM at 455 kHz
|
Vishay
|
| TSOP5700 |
IR Receiver for High Data Rate PCM at 455 kHz
|
VISAY[Vishay Siliconix]
|
| 106414-1201 |
QSFP to MPO Quad Data Rate PSM4 Active Optical Cable, 40 Gbps Data Rate, 2dB Loss Budget, Cable Length 1.0m
|
Molex Electronics Ltd.
|
| 106414-1403 |
QSFP to MPO Quad Data Rate PSM4 Active Optical Cable, 40 Gbps Data Rate, 4dB Loss Budget, Cable Length 3.0m
|
Molex Electronics Ltd.
|
| ADN2817ADN2818 ADN2818ACP-RL ADN2818ACP-RL7 ADN281 |
Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery ICs
Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery IC (With High Sensitivity Limiting Amp)
|
AD[Analog Devices]
Analog Devices, Inc.
|
| GS8170DD36C-333 GS8170DD36C-250 GS8170DD36C-300 GS |
18Mb x2Lp CMOS I/O Double Data Rate SigmaRAM 512K X 36 STANDARD SRAM, 2.1 ns, PBGA209
18Mb 1x2Lp CMOS I/O Double Data Rate SigmaRAM 35.71x2Lp的CMOS的I / O双数据速率SigmaRAM
|
GSI Technology, Inc.
|
| M13S5121632A-2S |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| W9725G6JB25I |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| M14D5121632A-2K |
Internal pipelined double-data-rate architecture; two data access per clock cycle
|
Elite Semiconductor Mem...
|
