| PART |
Description |
Maker |
| MC100EP131FAR2G |
3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential Clock; Package: 32 LEAD LQFP 7x7, 0.8P; No of Pins: 32; Container: Tape and Reel; Qty per Container: 2000 100E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQFP32
|
ON Semiconductor
|
| CD54AC113A CD54ACT112 CD54AC112 CD54ACT113A |
Dual J-K Flip-Flop with Set and Reset
Dual “J-K” Flip-Flop with Set and Reset
Dual “J-K?/a> Flip-Flop with Set and Reset
Dual “J-K Flip-Flop with Set and Reset
|
INTERSIL[Intersil Corporation]
|
| IN74ACT109N IN74ACT109 IN74ACT109D |
DUAL J-K FLIP-FLOP WITH SET AND RESET
|
INTEGRAL[Integral Corp.]
|
| SL74HC109 SL74HC109N SL74HC109D HC109 |
Dual J-K Flip-Flop with Set and Reset
|
System Logic Semiconductor Co., Ltd.
SLS[System Logic Semiconductor]
|
| SY10/100EL31 |
D Flip-Flop with Set & Reset D触发器的设置触发
|
Vishay Intertechnology, Inc.
|
| MC10EL31 MC100EL31 ON0666 |
From old datasheet system
D Flip-Flop With Set and Reset
|
ONSEMI[ON Semiconductor]
|
| MC100EP31 MC100EP31DG MC100EP31DR2G MC100EP31DTG M |
3.3V / 5V ECL D Flip−Flop with Set and Reset
|
ONSEMI[ON Semiconductor]
|
| GD54HCT76 GD54HC76 |
DUAL J-K FLIP-FLOP WITH SET AND RESET & CLEAR
|
ETC[ETC]
|
| 74LV109 74LV109D 74LV109DB 74LV109N 74LV109PW 74LV |
Dual JK flip-flop with set and reset; positive-edge trigger LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
From old datasheet system
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
|
| MC74HC74A ON1496 |
DUAL D FLIP-FLOP WITH SET AND RESET
From old datasheet system
|
ON Semi
|
