| PART |
Description |
Maker |
| LP61L1024S-12 LP61L1024X-12 LP61L1024V-12 LP61L102 |
128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM 128K的8.3V的高速低虚拟通道连接CMOS SRAM
128K X 8 BIT 3.3V HIGH SPEED LOW VCC CMOS SRAM 128K的83.3V的高速低虚拟通道连接CMOS SRAM
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AMIC Technology, Corp.
AMIC Technology Corporation
AMICC[AMIC Technology]
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| S34MS01G1 S34MS02G1 S34MS04G1 |
1-bit ECC, x8 and x16 I/O, 1.8V VCC SLC NAND Flash for Embedded
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Cypress Semiconductor
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| ST2378ETTR ST2378E ST2378E-06 ST2378EBJR |
8-bit dual supply 1.71V to 5.5V level translator with I/O VCC ± 15KV ESD protection
8-bit dual supply 1.71V to 5.5V level translator with I/O VCC 【 15KV ESD protection
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STMICROELECTRONICS[STMicroelectronics]
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| BC807-16-7 BC807-25-7 BC807-40-7 BC807 BC807-40 BC |
PNP SURFACE MOUNT TRANSISTOR
SH2 Series, 7086 Group, Two ADC circuits, 6-ch 16-bit MTU2, 3-ch 16-bit MTU2S, Port Output Enable, 2-ch CMT, UBC, 5v IO, 15 mA IO, BusTrace, AUD BP-112; Vcc= 3.0 to 5.5 volts, Temp= -20 to 85 C; Package: PLBG0112GA-A
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http://
DIODES[Diodes Incorporated]
Diodes Inc.
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| M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V
18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机
Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机
72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
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Renesas Electronics Corporation.
Renesas Electronics, Corp.
|
| KM62U256CLG-8L KM62U256CLG-10L |
32Kx8 bit Low Power AND Low Vcc CMOS Static RAM
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SAMSUNG SEMICONDUCTOR CO. LTD.
|
| CA3252 CA3252E CA3252M |
SH2 Series, 7145 Group, Two ADC circuits, 5-ch 16-bit MTU, 2-ch CMT, UBC, AUD FP-144F; Vcc= 3.0 to 3.6 volts, Temp= -40 to 85 C; Package: PLQP0144KB-A 四门控非反相功率驱动
Quad Gated Non-Inverting Power Driver
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Intersil, Corp.
INTERSIL[Intersil Corporation]
|
| CY14B104NA-ZSP20XCT CY14B104NA-ZSP20XIT CY14B104LA |
4 Mbit (512K x 8/256K x 16) nvSRAM; Organization: 256Kb x 16; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: TSOP 256K X 16 NON-VOLATILE SRAM, 20 ns, PDSO54
4 Mbit (512K x 8/256K x 16) nvSRAM; Organization: 512Kb x 8; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: FBGA
4 Mbit (512K x 8/256K x 16) nvSRAM; Organization: 256Kb x 16; Vcc (V): 2.7 to 3.6 V; Density: 4 Mb; Package: FBGA
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Cypress Semiconductor, Corp.
CYPRESS SEMICONDUCTOR CORP
|
| CA3242E CA3242 |
Quad-Gated Inverting Power Driver For Interfacing Low-Level Logic to High Current Load
SH2 Series, 7144 Group, Two ADC circuits, 5-ch 16-bit MTU, 2-ch CMT, UBC, AUD FP-112B; Vcc= 3.0 to 3.6 volts, Temp= -20 to 75 C; Package: PRQP0112JB-A 四门控逆变电源的驱动器的接口低级别逻辑高电流负
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INTERSIL[Intersil Corporation]
Intersil, Corp.
|
| MAX1603 MAX1603EAI MAX159BMJA MAX159BEPA MAX159AEU |
2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin MAX
2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin µMAX
Dual-Channel CardBus and PCMCIA VCC/VPP Power-Switching Networks
2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin ?MAX
2.7V Low-Power 2-Channel 108ksps Serial 10-Bit ADCs in 8-Pin ?MAX
KPSE 12C 8#20 4#16 PIN RECP
2.7V, Low-Power, 2-Channel, 108ksps, Serial 10-Bit ADCs in 8-Pin UMAX 2.7V、低功耗通道108ksps、串0位ADC引脚µMAX封装
CAP 33UF 100V ELECT TG SMD
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Maxim Integrated Produc...
MAXIM - Dallas Semiconductor
MAXIM[Maxim Integrated Products]
Maxim Integrated Products, Inc.
ADC
MAXIM INTEGRATED PRODUCTS INC
|
| M4-128/64-18VI M4-128/64-18YI M4-128N/64-18JI M4LV |
High Performance E 2 CMOS In-System Programmable Logic
High-performance E2CMOS in-system programmable logic, 3.3V Vcc, 128 macrocells, 64 I/Os, 14ns
High-performance E2CMOS in-system programmable logic, 5V Vcc, 128 macrocells, 64 I/Os, 14ns
High-performance E2CMOS in-system programmable logic, 3.3V Vcc, 192 macrocells, 96 I/Os, 14ns
High-performance E2CMOS in-system programmable logic, 5V Vcc, 256 macrocells, 128 I/Os, 14ns
High-performance E2CMOS in-system programmable logic, 3.3V Vcc, 256 macrocells, 128 I/Os, 14ns
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Lattice Semiconductor
|
| PMO-6022SN-42UQ |
Sensitivity Range -42 ± 3 dB RL = 2.2 k?Vcc = 2.0v (1 kHz 0 dB = 1 v/Pa)
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Mallory performance clu...
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