| PART |
Description |
Maker |
| MC10EP131 MC10EP131FA MC10EP131FAR2 MC100EP131FAR2 |
3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock 3.3 / 5V的ECL四D触发器设置，复位拖鞋和差分时
3.3V / 5V ECL Quad D Flip-Flop with Set Reset and Differential Clock
|
ONSEMI[ON Semiconductor]
|
| TC4044BF TC4044BFN TC4044BP E004212 |
From old datasheet system
QUAD 3-STATE R/S LATCH(Quad NAND R/S Latch)
|
TOSHIBA[Toshiba Semiconductor]
|
| 74AUP1G74GD 74AUP1G74GM125 |
Low-power D-type flip-flop with set and reset; positive-edge trigger
Low-power D-type flip-flop with set and reset; positive-edge trigger; Package: SOT902-1 (XQFN8U); Container: Reel Pack, Reverse, Reverse
|
NXP Semiconductors
|
| HCF4044 HCF4044BM1 |
4000/14000/40000 SERIES, LOW LEVEL TRIGGERED R-S LATCH, TRUE OUTPUT, PDSO16
QUAD NAND 3-STATE R-S LATCH
|
STMICROELECTRONICS
ST Microelectronics
|
| MC10H106 MC100EL29DWR2 MC10H117 MC10H117FN MC100EP |
Triple 4-3-3-Input NOR Gate
5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset
Dual 2-Wide 2-3-Input OR-AND/OR-AND-Invert Gate
3.3V / 5V ECL Differential Receiver/Driver with Variable Output Swing
5V ECL 2-Input XOR/XNOR
4-Wide OR-AND/OR-ANDbar Gate
5V ECL 1:2 Differential Fanout Buffer
3.3V / 5V ECL 6-Bit Differential Register with Master Reset
3.3V ECL Triple D-Type Flip-Flop with Set and Reset
3.3V / 5V ECL ÷2 Divider
5V ECL Differential Data and Clock D Flip-Flop
|
ON Semiconductor
|
| CD4042BMS FN3310 |
CMOS Quad Clocked “D” Latch
From old datasheet system
CMOS Quad Clocked "N" Latch
CMOS Quad Clocked D Latch
|
INTERSIL[Intersil Corporation]
|
| MC100EL31D MC100EL31DG MC100EL31DR2 MC100EL31DR2G |
5 V ECL D Flip-Flop With Set and Reset
|
ONSEMI[ON Semiconductor]
|
| CD54AC109 CD54AC103A CD54ACT109 CD54ACT103A CD54AC |
Dual J-K Flip-Flop with Set and Reset
|
INTERSIL[Intersil Corporation]
|
| MC74VHC74-D MC74VHC74MEL MC74VHC74DR2 MC74VHC74DTR |
Dual D-Type Flip-Flop with Set and Reset
|
ON Semiconductor
|
| GD54HCT76 GD54HC76 |
DUAL J-K FLIP-FLOP WITH SET AND RESET & CLEAR
|
ETC[ETC]
|
