| PART |
Description |
Maker |
| AS7C32098A AS7C32098A-20TIN AS7C32098A-10TC AS7C32 |
Hex D-Type Flip-Flops With Clear 16-TSSOP -40 to 85 128K X 16 STANDARD SRAM, 10 ns, PDSO44
Quadruple D-Type Flip-Flops With Clear 16-TVSOP -40 to 85
Quadruple D-Type Flip-Flops With Clear 16-SSOP -40 to 85
Quadruple D-Type Flip-Flops With Clear 16-SOIC -40 to 85
Quadruple D-Type Flip-Flops With Clear 16-SO -40 to 85
SRAM - 3.3V Fast Asynchronous
3.3 V 128K x 16 CMOS SRAM
|
Alliance Semiconductor, Corp.
ALSC[Alliance Semiconductor Corporation]
|
| LC866408 LC866412 LC866416 LC866420 LC866424 SANYO |
Octal D-Type Flip-Flops With Clear 20-SO -40 to 85
Octal D-Type Flip-Flops With Clear 20-SOIC -40 to 85
Octal Bus Transceivers With 3-State Outputs 20-VQFN -40 to 85
8-Bit Single Chip Microcontroller with the UVEPROM
|
http://
Sanyo Electric Co.,Ltd.
|
| HCTS109HMSR HCTS109KMSR HCTS109K HCTS109D HCTS109D |
Dual Positive-Edge-Triggered D-Type- Flip-Flops With Clear And Preset 14-CDIP -55 to 125 辐射加固双JK触发器拖
Radiation Hardened Dual JK Flip Flop
From old datasheet system
|
Intersil, Corp.
INTERSIL[Intersil Corporation]
|
| HD74HC73P HD74HC73FPEL HD74HC73RPEL |
Dual J-K Flip-Flops (with Clear)
|
Renesas Electronics Corporation
|
| MM74C73 MM74C73N MM74C76M MM74C76N |
Dual J-K Flip-Flops with Clear and Preset
|
FAIRCHILD[Fairchild Semiconductor]
|
| UT54ACTS74E |
Dual D Flip-Flops with Clear and Preset
|
Aeroflex Circuit Techno...
|
| HD74LV74A |
Dual D-type Flip-Flops with Preset and Clear
|
Hitachi Semiconductor
|
| HD74LV74A HD74LV74AFPEL HD74LV74ARPEL HD74LV74ATEL |
Dual D-type Flip Flops with Preset and Clear
|
Renesas Electronics Corporation
|
| M27W201-80K6TR M27W201-200NZ6TR M27W201-80NZ6TR M2 |
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
Test Spring Probe; Current Rating:3A; Leaded Process Compatible:Yes; Length:0.060"; Peak Reflow Compatible (260 C):No; Tip/Nozzle Style:90 Concave RoHS Compliant: Yes 2兆位56Kb × 8低压紫外线可擦写可编程只读存储器和OTP存储
Triple 3-Input Positive-AND Gates 14-SO 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SO 0 to 70
Triple 3-Input Positive-AND Gates 14-PDIP 0 to 70
Triple 3-Input Positive-AND Gates 14-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70
2 Mbit 256Kb x 8 Low Voltage UV EPROM and OTP EPROM
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
|
STMicroelectronics N.V.
意法半导
STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics
|
| HD74LS107A HD74LS107AFPEL HD74LS107AP |
Dual J-K Negative-edge-triggered Flip-Flops (with Clear)
|
Renesas Electronics Corporation
|
| 74VHC112MTC 74VHC112SJ 74VHC112 74VHC112M 74VHC112 |
Dual J-K Flip-Flops with Preset and Clear
From old datasheet system
|
FAIRCHILD[Fairchild Semiconductor]
|
| DM7476N |
Dual Master-Slave J-K Flip-Flops with Clear/ Preset/ and Complementary Outputs
Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs
|
FAIRCHILD[Fairchild Semiconductor]
|
