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  pecl lvcmos Datasheet PDF File

For pecl lvcmos Found Datasheets File :: 519    Search Time::0.985ms    
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    MC12439 MC12439FN

Motorola, Inc
MOTOROLA[Motorola Inc]
Part No. MC12439 MC12439FN
OCR Text ...400 to 800MHz. The differential pecl output can be configured to be the VCO frequency divided by 1, 2, 4, or 8. With the output configured t...lvcmos input can also be used as the PLL reference. The reference is selected via the XTAL_SEL input...
Description HIGH FREQUENCY PLL CLOCK GENERATOR

File Size 129.32K  /  11 Page

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    CYPRESS SEMICONDUCTOR CORP
Part No. CY29773AXI CY29773AXIT
OCR Text ...en ref_sel tclk_sel tclk0 tclk1 pecl _ cl k pecl_clk# avdd fb_sel1 sync vss qc0 vddqc qc1 selc0 selc1 qc2 vddqc qc3 vss inv_clk selb1 selb0 ...lvcmos lvcmos/lvttl reference clock input . 10 tclk1 i, pu lvcmos lvcmos/lvttl reference clock input...
Description 29773 SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52

File Size 223.74K  /  13 Page

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    PCK953BD PCK953

NXP Semiconductors
PHILIPS[Philips Semiconductors]
Part No. PCK953BD PCK953
OCR Text pecl input/9 CMOS output 3.3 V PLL clock driver Product specification Supersedes data of 2000 Oct 25 ICL03 -- PC Motherboard ICs; Logic Pro...lvcmos or LVTTL compatible levels, while the outputs provide lvcmos levels with the ability to drive...
Description 50-125 MHz pecl input/9 CMOS output 3.3 V PLL clock driver

File Size 65.55K  /  8 Page

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    EXAR CORP
Part No. K39351CQ
OCR Text ...elb selc oe qa qc 0 qc 1 1 0 pecl pecl r ef_sel vdd qd 4 qd 0 qd 1 qd 2 qd 3 q b 1 0 seld xrk39351 xr 3.3v or 2.5v, 9-output pll clo...lvcmos reference clock input 31 pll_en input pull-up selects pll or pll-bypass (test mode) operation...
Description 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER

File Size 74.56K  /  12 Page

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    NBSG53AMNG NBSG53AMNR2G NBSG53A_06 NBSG53ABA NBSG53ABAEVB NBSG53ABAR2 NBSG53AMN NBSG53AMNR2 NBSG53A06

ONSEMI[ON Semiconductor]
Part No. NBSG53AMNG NBSG53AMNR2G NBSG53A_06 NBSG53ABA NBSG53ABAEVB NBSG53ABAR2 NBSG53AMN NBSG53AMNR2 NBSG53A06
OCR Text ...and accept NECL (Negative ECL), pecl (Positive ECL), lvcmos/LVTTL, CML, or LVDS. The OLS* input is used to program the peak-to-peak output amplitude between 0 and 800 mV in five discrete steps. The RESET and SELECT inputs are single-ended a...
Description 2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip−Flop/Clock Divider with Reset and OLS

File Size 150.51K  /  18 Page

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    MOTOROLA INC
Part No. MPC9299FN
OCR Text pecl clock synthesizer the mpc9229 is a 3.3v compatible, pll based clock synthesizer targeted for high performance clock generation in mid-r...lvcmos compatible control inputs ? on-chip crystal oscillator for reference fr equency generation ? ...
Description 400 MHz, OTHER CLOCK GENERATOR, PQCC28

File Size 183.62K  /  12 Page

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    EXAR[Exar Corporation]
Part No. XRK39351IQ XRK39351_0611 XRK39351 XRK39351CQ XRK393510611
OCR Text ...-Lead TQFP Packaging /2 TCLK pecl pecl FB_IN VDD 0 QA 1 1 Ref 0 FB 0 /4 PLL 1 0 QB 1 /8 PLL_EN SELA SELB SELC SELD ...lvcmos reference clock input Selects PLL or PLL-bypass (test mode) operation Selects primary referen...
Description 3.3V OR 2.5V, 9-OUTPUT PLL CLOCK DRIVER

File Size 72.60K  /  12 Page

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    IDT
Part No. MPC940L
OCR Text ...gurations pin i/o type function pecl_clk input lvpecl reference clock input pecl_clk lvcmos_clk input lvcmos alternative reference clock input lvcmos_clk_sel input lvcmos selects clock source q0?q17 output lvcmos clock outputs v cco supply ...
Description LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP

File Size 1,092.46K  /  11 Page

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