| |
|
 |
pmc
|
| Part No. |
2001577
|
| OCR Text |
....8 Internal HDLC Controller and timeslot One (E1 Mode) .....................................9 Internal HDLC Controller and Data in Sa-bit Positions (E1 Mode) ...................10 Description of NmNI............................................ |
| Description |
From old datasheet system
|
| File Size |
193.53K /
16 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
Zarlink
|
| Part No. |
MT8979 133
|
| OCR Text |
...os in the high order quartet of timeslot 16 frame 0, i.e., once every 16 frames (see Figure 5). The CEPT format has four signalling bits, A, B, C and D. Signalling bits for all 30 information channels are transmitted in timeslot 16 of frame... |
| Description |
ISO-CMOS ST-BUS? FAMILY
From old datasheet system
|
| File Size |
612.20K /
29 Page |
View
it Online |
Download Datasheet |
| |
|
|
Zarlink
|
| Part No. |
MT9161B 196
|
| OCR Text |
...dge of the bit clock during the timeslot defined by STB, or according to standard ST-BUS timing. Data Input. A digital input for 8 bit wide channel data received from the Layer 1 transceiver. Data is sampled on the falling edge of the bit c... |
| Description |
ISO2-CMOS
From old datasheet system
|
| File Size |
414.61K /
30 Page |
View
it Online |
Download Datasheet |
| |
|
|
Zarlink
|
| Part No. |
MT9080B 170
|
| OCR Text |
...ith the rising edge in the next timeslot (see Fig. 24 for applicable timing in different modes). Message Enable. When tied high the data latched in on the address bus is clocked out on D0o-D15o. When ME is tied low, the contents of the addr... |
| Description |
CMOS
From old datasheet system
|
| File Size |
455.92K /
24 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
