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IDT
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Part No. |
77V126_DS_78621 IDT77V126 IDT77V126L200TFI IDT77V126L200TFI8
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OCR Text |
...m. A state machine monitors the received symbols and asserts the "Good Signal" status bit when a valid signal is being received. "Good Signal" is deasserted and the receive FIFO is disabled when the signal is lost. This is sometimes referre... |
Description |
1 Channel 200Mbps PHY, U1 ATM 200 Mbps backplane PHY with UTOPIA-1 interface From old datasheet system
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File Size |
232.47K /
30 Page |
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it Online |
Download Datasheet
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OKI electronic eomponets
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Part No. |
82C51A
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OCR Text |
... CPU and sends status words and received data to CPU. RESET (Input terminal) A "High" on this input forces the MSM82C51A-2 into "reset status." The device waits for the writing of "mode instruction." The min. reset width is six clock inputs... |
Description |
UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER
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File Size |
203.88K /
27 Page |
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it Online |
Download Datasheet
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Price and Availability
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