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For masks Found Datasheets File :: 2378    Search Time::1.36ms    
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    K4S561632A K4S561632A-TC_L1H K4S561632A-TC_L1L K4S561632A-TC_L75 K4S561632A-TC_L80 K4S561632A-TC/L1H K4S561632A-TC/L1L K

SAMSUNG SEMICONDUCTOR CO. LTD.
SAMSUNG[Samsung semiconductor]
Samsung Electronic
Part No. K4S561632A K4S561632A-TC_L1H K4S561632A-TC_L1L K4S561632A-TC_L75 K4S561632A-TC_L80 K4S561632A-TC/L1H K4S561632A-TC/L1L K4S561632A-TC/L75 K4S561632A-TC/L80
OCR Text ... inputs except CLK, CKE and DQM masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multi...
Description 256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL

File Size 125.82K  /  10 Page

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    K4S561632B K4S561632B-TC_L1L K4S561632B-TC_L1H K4S561632B-TC_L75 K4S561632B-TC/L1L K4S561632B-TC/L75 K4S561632B-TC/L1H

Samsung Semiconductor Co., Ltd.
SAMSUNG[Samsung semiconductor]
Samsung Electronic
Part No. K4S561632B K4S561632B-TC_L1L K4S561632B-TC_L1H K4S561632B-TC_L75 K4S561632B-TC/L1L K4S561632B-TC/L75 K4S561632B-TC/L1H
OCR Text ... inputs except CLK, CKE and DQM masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multi...
Description 256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL 56Mbit SDRAM米16 × 4银行同步DRAM LVTTL

File Size 130.19K  /  11 Page

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    K4S561632D K4S561632D-TC_L75 K4S561632D-TC_L1H K4S561632D-TC_L1L K4S561632D-TC_L60 K4S561632D-TC_L7C K4S561632D-TC/L1H K

SAMSUNG[Samsung semiconductor]
Samsung Electronic
Part No. K4S561632D K4S561632D-TC_L75 K4S561632D-TC_L1H K4S561632D-TC_L1L K4S561632D-TC_L60 K4S561632D-TC_L7C K4S561632D-TC/L1H K4S561632D-TC/L1L K4S561632D-TC/L60 K4S561632D-TC/L75 K4S561632D-TC/L7C K4S561632D-TC75000
OCR Text ... inputs except CLK, CKE and DQM masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multi...
Description 256Mbit SDRAM 4M x 16bit x 4 Banks Synchronous DRAM LVTTL

File Size 59.61K  /  11 Page

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    MCP2510 MCP2510-EP MCP2510-ESO MCP2510-EST MCP2510-IP MCP2510-ISO MCP2510-IST

Microchip Technology
Part No. MCP2510 MCP2510-EP MCP2510-ESO MCP2510-EST MCP2510-IP MCP2510-ISO MCP2510-IST
OCR Text ...rs - Two full acceptance filter masks - Three transmit buffers with prioritization and abort features - Loop-back mode for self test operation * Hardware Features - High Speed SPI Interface (5 MHz at 4.5V I temp) - Supports SPI modes 0,0 an...
Description Stand-Alone CAN Controller with SPI Interface

File Size 606.30K  /  76 Page

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    MS82V16520

OKI[OKI electronic componets]
Part No. MS82V16520
OCR Text ...CKE, DQM0, DQM1, DQM2 and DQM3. masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle...
Description 262,144-Word x 32-Bit x 2-Bank Synchronous Graphics RAM

File Size 838.09K  /  67 Page

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    HA13609ANT

HITACHI[Hitachi Semiconductor]
Part No. HA13609ANT
OCR Text ...25% (@MD4 = 0) 3. This function masks the current limiter input (pin 27) (incorrect operation due to the recovery current). See page 20 for details. 4. The PLL output setting indicates a change relative to 3.5 Vp-p. See the electrical chara...
Description Three-Phase Brushless Motor Driver

File Size 141.12K  /  31 Page

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    KM48S8030D KM48S8030DT-GFA KM48S8030DT-GFL KM48S8030DT-GF8

Samsung Semiconductor Co., Ltd.
SAMSUNG SEMICONDUCTOR CO. LTD.
SAMSUNG[Samsung semiconductor]
Samsung Electronic
Part No. KM48S8030D KM48S8030DT-GFA KM48S8030DT-GFL KM48S8030DT-GF8
OCR Text ... inputs except CLK, CKE and DQM masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multi...
Description 2M x 8bit x 4 banks synchronous DRAM, 3.3V power supply, LVTTL, 125MHz
2M x 8bit x 4 banks synchronous DRAM, 3.3V power supply, LVTTL, 133MHz
64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL 64Mbit SDRAM00万8位4银行同步DRAM LVTTL
2M x 8bit x 4 banks synchronous DRAM, 3.3V power supply, LVTTL, 100MHz

File Size 116.15K  /  11 Page

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    KM48S8030 KM48S8030C KM48S8030CT-G_FA KM48S8030CT-G/FA

Samsung Semiconductor Co., Ltd.
SAMSUNG[Samsung semiconductor]
Samsung Electronic
Part No. KM48S8030 KM48S8030C KM48S8030CT-G_FA KM48S8030CT-G/FA
OCR Text ... inputs except CLK, CKE and DQM masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multi...
Description 2M x 8Bit x 4 Banks Synchronous DRAM 200万8位4银行同步DRAM

File Size 81.46K  /  8 Page

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    MK2716 MK2716S MK2716STR

ICST[Integrated Circuit Systems]
Part No. MK2716 MK2716S MK2716STR
OCR Text ...low power CMOS process * Custom masks easily and quickly made Block Diagram VDD GND 2 SEL 27 MHz crystal or X1 clock Clock Buffer X2 Clock Synthesis and Control Circuitry Output Buffer CLK 74.17582418 MHz or 74.2500 MHz ...
Description HDTV Clock Synthesizer

File Size 57.26K  /  4 Page

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For masks Found Datasheets File :: 2378    Search Time::1.36ms    
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