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ICS
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Part No. |
M2006-11 M2006-21 M2006-11-622.0800
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OCR Text |
...LVPECL, as well as single-ended lvcmos, LVTTL
Figure 1: Pin Assignment
Example Input / Output Frequency Combinations
Input Clock VCSO Output (MHz) Freq1 (MHz) Freq (MHz) 19.44 19.53125 622.08 625.00 622.08 155.52 156.25 Gigabit Ether... |
Description |
PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), CQCC36 SAW PLL for Frequency Translation with Add/Drop feature and Hitless Switching option
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File Size |
312.67K /
14 Page |
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ON Semiconductor
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Part No. |
NB7L216
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OCR Text |
...l), positive ecl (pecl), lvttl, lvcmos, cml, or lvds. outputs are reduced swing ecl (rsecl), 400 mv. the v bb pin is internally generated voltage supply available to this device only. the v bb is used as a reference voltage for single ? ... |
Description |
2.5V/3.3V, 12Gb/s Multi Level Clock/Data Input to RSECL, High Gain Receiver/Buffer/Translator with Internal Termination(带内部端口的2.5V/3.3V,12Gb/s多级时钟/数据输入到RSECL,高增益接收器/缓冲转换
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File Size |
470.57K /
12 Page |
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it Online |
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Integrated Device Techn...
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Part No. |
IDT8T79S828I-08
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OCR Text |
...ximum input frequency: 1.5ghz ? lvcmos control inputs ? qxx 1 edge aligned to qxx n edge ? individual output divider control via serial inte...lvttl interface levels. 2 miso output serial control port mode data output. lvcmos/lvttl interface ... |
Description |
1-to-8 Differential to Universal Output Clock Divider/Fanout Buffer
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File Size |
444.28K /
28 Page |
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it Online |
Download Datasheet |
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Integrated Device Techn...
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Part No. |
IDT8T79S818I-08
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OCR Text |
...ximum input frequency: 1.5ghz ? lvcmos control inputs ? qxx 1 edge aligned to qxx n edge ? individual output divider control via serial inte...lvttl interface levels. 2 miso output serial control port mode data output. lvcmos/lvttl interface ... |
Description |
Four banks of two low skew outputs
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File Size |
457.22K /
28 Page |
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it Online |
Download Datasheet |
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Price and Availability
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