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    K5P2880YCM

Samsung Electronic
SAMSUNG[Samsung semiconductor]
Part No. K5P2880YCM
OCR Text ...e Register. 00h Command(Read) : defines the starting address of the 1st half of the register. 01h Command(Read) : defines the starting address of the 2nd half of the register. * A8 is set to "Low" or "High" by the 00h or 01h Command. * L mu...
Description Multi-Chip Package MEMORY 128M Bit 16Mx8 Nand Flash Memory / 8M Bit 1Mx8/512Kx16 Full CMOS SRAM

File Size 549.77K  /  29 Page

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    MPC9443

Motorola, Inc
Part No. MPC9443
OCR Text ...nd input circuitry. VCC voltage defines the input threshold and levels VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels VCCB is the positive power supply of the bank B outputs. VCCB voltage ...
Description 2.5V AND 3.3V LVCMOS CLOCK FANOUT BUFFER

File Size 331.29K  /  16 Page

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    MPC9446

Motorola, Inc.
Part No. MPC9446
OCR Text ...nd input circuitry. VCC voltage defines the input threshold and levels VCCA is the positive power supply of the bank A outputs. VCCA voltage defines bank A output levels VCCB is the positive power supply of the bank B outputs. VCCB voltage ...
Description 2.5V and 3.3V LVCMOS Clock Fanout Buffer

File Size 216.43K  /  12 Page

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    EM658160 EM658160TS-33 EM658160TS-35 EM658160TS-4 EM658160TS-5 EM658160TS-6 EM658160TS-7 EM658160TS-8

ETRON[Etron Technology, Inc.]
ETRON[Etron Technology Inc.]
Part No. EM658160 EM658160TS-33 EM658160TS-35 EM658160TS-4 EM658160TS-5 EM658160TS-6 EM658160TS-7 EM658160TS-8
OCR Text ...modes. Bank Select: BS0 and BS1 defines to which bank the BankActivate, Read, Write, or BankPrecharge command is being applied. Address Inputs: A0-A11 are sampled during the BankActivate command (row address A0-A11) and Read/Write command (...
Description 4M x 16 DDR Synchronous DRAM (SDRAM)

File Size 154.94K  /  26 Page

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    GAL16V811111 GAL16V8B-10LJ GAL16V8B-10LJI GAL16V8B-10LP GAL16V8B-10LPI GAL16V8B-15LJ GAL16V8B-15LJI GAL16V8B-15LP GAL16V

LATTICE[Lattice Semiconductor]
Part No. GAL16V811111 GAL16V8B-10LJ GAL16V8B-10LJI GAL16V8B-10LP GAL16V8B-10LPI GAL16V8B-15LJ GAL16V8B-15LJI GAL16V8B-15LP GAL16V8B-15QJ GAL16V8B-15QP GAL16V8B-25LJ GAL16V8B-25LJI GAL16V8B-25LP GAL16V8B-25LPI GAL16V8B-25QJ GAL16V8B-25QJI GAL16V8B-25QP GAL16V8B-25QPI GAL16V8B-5LPI GAL16V8B-7LJ GAL16V8B-7LP GAL16V8C-5LJ GAL16V8C-5LP GAL16V8C-7LJ GAL16V8C-7LJI GAL16V8C-7LP GAL16V8C-7LPI
OCR Text ... Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this output configuration. - Pin 1 controls common CLK for the registered outputs. - Pin 11 controls common OE for the registered...
Description High Performance E2CMOS PLD Generic Array Logic

File Size 391.81K  /  23 Page

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    GAL16V8 GAL16V8D GAL16V8D-10LJ GAL16V8D-10LJI GAL16V8D-10LP GAL16V8D-10LPI GAL16V8D-10LS GAL16V8D-10QJ GAL16V8D-10QP GAL

Lattice Semiconductor Corp
LATTICE[Lattice Semiconductor]
Part No. GAL16V8 GAL16V8D GAL16V8D-10LJ GAL16V8D-10LJI GAL16V8D-10LP GAL16V8D-10LPI GAL16V8D-10LS GAL16V8D-10QJ GAL16V8D-10QP GAL16V8D-15LJ GAL16V8D-15LJI GAL16V8D-15LP GAL16V8D-15LPI GAL16V8D-15LS GAL16V8D-15QJ GAL16V8D-15QP GAL16V8D-20QJI GAL16V8D-20QPI GAL16V8D-25LJ GAL16V8D-25LJI GAL16V8D-25LP GAL16V8D-25LPI GAL16V8D-25LS GAL16V8D-25QJ GAL16V8D-25QJI GAL16V8D-25QP GAL16V8D-3LJ GAL16V8D-10LJNBSP GAL16V8D-7LJI GAL16V8-25LNC GAL16V8D-25QPI GAL16V8D-5LJ GAL16V8D-7LJ GAL16V8D-7LP GAL16V8D-7LS GAL16V8D-7LPI GAL16V8D-20LD/833 GAL16V8D-20LR/833 GAL16V8D-10LD/833 GAL16V8D-7LD/833 GAL16V8D-7LR/833
OCR Text ... Mode - SYN=0. - AC0=1. - XOR=0 defines Active Low Output. - XOR=1 defines Active High Output. - AC1=0 defines this output configuration. - Pin 1 controls common CLK for the registered outputs. - Pin 11 controls common OE for the registered...
Description High Performance E2CMOS PLD Generic Array Logic
SIMPLE-EEPLD,PAL-TYPE,CMOS,LDCC,20PIN,PLASTIC
Electrically-Erasable PLD

File Size 312.07K  /  22 Page

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    WED3DL328V10BC WED3DL328V10BI WED3DL328V8BC WED3DL328V8BI WED3DL328V7BI WED3DL328V WED3DL328V7BC

WEDC[White Electronic Designs Corporation]
Part No. WED3DL328V10BC WED3DL328V10BI WED3DL328V8BC WED3DL328V8BI WED3DL328V7BI WED3DL328V WED3DL328V7BC
OCR Text ...k Activate command cycle, A0-11 defines the row address (RA0-11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-8 defines the column address (CA0-8) when sampled at the rising clock edge. In addition to the ...
Description 8Mx32 SDRAM

File Size 1,036.74K  /  27 Page

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    16000-3 16000-4 16003-2 16000-2 16003-3 16003-4 16500-1 16500-2 16500-3 16504-1 16504-2 16504-3

Cooper Bussmann, Inc.
Part No. 16000-3 16000-4 16003-2 16000-2 16003-3 16003-4 16500-1 16500-2 16500-3 16504-1 16504-2 16504-3
OCR Text ...6204 where: ? the prefix 16204 defines the blocks lineside and loadside characteristics (i.e., conductor port per pole that accepts 2/0 - #14 cu, or 2/0 - #12 al conductors). ? the suffix 3 in this example defines this as a three-pole...
Description    Splicer blocks

File Size 1,025.13K  /  4 Page

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