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FUJITSU LTD
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Part No. |
MBM29DL320BF70TR
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OCR Text |
... without the wait. to eliminate bus contention the device has separate chip enable (ce ) , write enable (we ) and output enable (oe ) contro...register using standard microprocessor write timings. register contents serve as input to an interna... |
Description |
2M X 16 FLASH 3V PROM, 70 ns, PDSO48
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File Size |
346.89K /
71 Page |
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INTEGRATED SILICON SOLUTION INC
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Part No. |
IS61LPS25632T-200TQI
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OCR Text |
... to the two lsbs of the address bus. a synchronous address inputs clk synchronous clock adsp synchronous processor address status adsc synch...register. the register between tdi and tdo is chosen by the instruction loaded into the tap instruct... |
Description |
256K X 32 CACHE SRAM, 3.1 ns, PQFP100
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File Size |
176.18K /
29 Page |
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ALLIANCE SEMICONDUCTOR CORP
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Part No. |
AS7C33128NTD36A-100BC AS7C33128NTD36A-166TQC
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OCR Text |
... ?1 architecture for effi cient bus operation fast clock speeds to 166 mhz in lvttl/lvcmos fast clock to data access: 3.5/4.0/5.0 ns fa...register output register dq [a:d] 17 17 clk ce0 ce1 ce2 a[16:0] oe clk cen control clk logic data d ... |
Description |
128K X 36 ZBT SRAM, 12 ns, PQFP100 128K X 36 ZBT SRAM, 9 ns, PQFP100
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File Size |
161.04K /
10 Page |
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Download Datasheet |
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Price and Availability
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