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INTERSIL[Intersil Corporation]
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| Part No. |
ACS00KMSR ACS00K FN3563 ACS00MS ACS00D ACS00DMSR ACS00HMSR
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| OCR Text |
...or functional tests, VO 4.0V is recognized as a logic "1", and VO 0.5V is recognized as a logic "0".
Spec Number 2
518813
Specifications ACS00MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS (NOTES 1, 2) CONDITIONS VCC = 4.5V... |
| Description |
Radiation Hardened Quad 2-Input NAND Gate
From old datasheet system
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| File Size |
67.98K /
8 Page |
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it Online |
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CYPRESS[Cypress Semiconductor]
Cypress Semiconductor Corp.
Cypress Semiconductor, Corp.
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| Part No. |
CY7C1350G-250BGI CY7C1350G CY7C1350G-100AXC CY7C1350G-100AXI CY7C1350G-100BGC CY7C1350G-100BGI CY7C1350G-133AXC CY7C1350G-133AXI CY7C1350G-133BGC CY7C1350G-133BGI CY7C1350G-166AXC CY7C1350G-166AXI CY7C1350G-166BGC CY7C1350G-166BGI CY7C1350G-200AXC CY7C1350G-200AXI CY7C1350G-200BGC CY7C1350G-200BGI CY7C1350G-225AXC CY7C1350G-225AXI CY7C1350G-225BGC CY7C1350G-225BGI CY7C1350G-250AXC CY7C1350G-250AXI CY7C1350G-250BGC
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| OCR Text |
...qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. Chip Enable 2 Input, active HIGH. Sampl... |
| Description |
4-Mbit (128K x 36) Pipelined SRAM with NoBL(TM) Architecture
Mechanism, 2-inch wide, compact, Easy Load and platen detect
Mechanism, 2-inch wide, Hi-speed, compact Easy Load
Parallel Mini Interface Board with cutter controller for 6x8MCL35x
Mechanism, ELM w/low profile cutter (full or partial cut)
Mechanism, 2-inch wide, Hi-speed, compact, rear feed and platen detect 128K X 36 ZBT SRAM, 2.6 ns, PQFP100
Mechanism, 2-inch wide, compact Easy Load, 3V logic 128K X 36 ZBT SRAM, 2.6 ns, PBGA119
4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture 128K X 36 ZBT SRAM, 4 ns, PBGA119
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| File Size |
295.74K /
15 Page |
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it Online |
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CYPRESS[Cypress Semiconductor]
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| Part No. |
CY7C1378B-166AC CY7C1378B
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| OCR Text |
...qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. Chip Enable 2 Input, active HIGH. Sampl... |
| Description |
9-Mbit (256K x 32) Pipelined SRAM with NoBL(TM) Architecture
9-Mbit (256K x 32) Pipelined SRAM with NoBL Architecture
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| File Size |
245.94K /
14 Page |
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it Online |
Download Datasheet |
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Intersil, Corp.
INTERSIL[Intersil Corporation]
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| Part No. |
ACTS08MS ACTS08DMSR FN3994 ACTS08D ACTS08HMSR ACTS08K ACTS08KMSR
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| OCR Text |
...er functional tests, VO 4.0V is recognized as a logic "1", and VO 0.5V is recognized as a logic "0".
Spec Number 2
518851
Specifications ACTS08MS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 9 10, 11 9 10, ... |
| Description |
Radiation Hardened Quad 2-Input AND Gate 辐射加固输入与门
Radiation Hardened Quad 2-Input AND Gate ACT SERIES, QUAD 2-INPUT AND GATE, CDIP14
From old datasheet system
AND Gate, 2-Input, Quad, TTL Inputs, Rad-Hard, Advanced Logic, CMOS
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| File Size |
76.61K /
8 Page |
View
it Online |
Download Datasheet |
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