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Integrated Device Technology, Inc.
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| Part No. |
ICSSSTUB32871A
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| OCR Text |
...17 d18 v dd v dd q17 q18 t d1 9 d20 v dd q1 9 q20 123456 dcke1 v ref
3 1186g?04/16/07 icssstub32871a general description this 27-bit 1:1 registered buffer with parity is designed for 1.7v to 1.9v v dd operation. all clock and data input... |
| Description |
27-Bit Registered Buffer for DDR2 27位注册缓冲DDR2内存
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| File Size |
203.43K /
18 Page |
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it Online |
Download Datasheet
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IDT
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| Part No. |
ICSSSTUAF32868B
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| OCR Text |
...28 when c = 0; or d1-d12, d17-d20, d22, d24-d28 wh en c = 1) and indicates whether a parity error has occurred on the open-drain qerr pin (active low). the convention is even parity, i.e., valid parity is defined as an even number of ... |
| Description |
28-BIT CONFIGURABLE REGISTERED BUFFER
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| File Size |
489.18K /
22 Page |
View
it Online |
Download Datasheet |
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IDT
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| Part No. |
ICSSSTUAF32868A
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| OCR Text |
...28 when c = 0; or d1-d12, d17-d20, d22, d24-d28 wh en c = 1) and indicates whether a parity error has occurred on the open-drain qerr pin (active low). the convention is even parity, i.e., valid parity is defined as an even number of ... |
| Description |
28-BIT CONFIGURABLE REGISTERED BUFFER
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| File Size |
489.14K /
22 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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