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Cypress Semiconductor Corp.
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| Part No. |
CY7C1330 7C1330
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| OCR Text |
...t sequence is controlled by the adv input. Byte write operations are qualified with the four Byte Write Select (BW[0-3]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are co... |
| Description |
64K x 32 Synchronous-Pipelined Cache RAM(64K x 32 同步流水线式高速缓冲存储器 RAM)
From old datasheet system
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| File Size |
316.54K /
16 Page |
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it Online |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1332 CY7C1331 7C1331
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| OCR Text |
advANCED INFORMATION
CY7C1331 CY7C1332
64K x 18 Synchronous Cache 3.3V RAM
Features
* Supports 66-MHz PentiumTM processor cache systems with zero wait states * Single 3.3V power supply * 64K by 18 common I/O * Fast clock-to-output t... |
| Description |
64K x 18 Synchronous Cache 3.3V RAM(3.3V 64K x 18 同步高速缓冲存储器 RAM) 64K的18同步高速缓.3V的内存电压（3.3V 64K的18同步高速缓冲存储器的RAM
From old datasheet system
64K x 18 SynchronousCache 3.3V RAM
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| File Size |
312.37K /
13 Page |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1333 7C1333 CY7C1333-66AC CY7C1333-50AC
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| OCR Text |
...LK D CE Data-In REG. Q
32
adv/LD A[15:0] CEN CE1 CE2 CE3 WE BWS[3:0] Mode
32 16
CONTROL and WRITE LOGIC
16
64KX32 MEMORY ARRAY
32 32
DQ[31:0]
OE
Selection Guide
7C1333-66 Maximum Access Time (ns) Maximum Operating... |
| Description |
64Kx32 Flow-Thru SRAM with NoBL Architecture(B>NoBL结构4Kx32流通式 SRAM)
64Kx32 Flow-Thru SRAM with NoBL⑩ Architecture
From old datasheet system
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| File Size |
179.79K /
12 Page |
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it Online |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1334 7C1334
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| OCR Text |
...E D Data-In REG. Q
32
32
adv/LD A[15:0] CEN CE1 CE 2 CE 3 WE BWS[3:0] CLK OOUTPUT REGISTERS and LOGIC
16
CONTROL and WRITE LOGIC
16
64KX32 MEMORY ARRAY
32
32
DQ[31:0]
OE
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Selection Guide
7C1334-133 Maximum... |
| Description |
64Kx32 Flow-Thru SRAM with NoBL Architecture(B>NoBL结构4Kx32流通式 SRAM)
From old datasheet system
64Kx32 Pipelined SRAM with NoBL Architecture
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| File Size |
183.37K /
11 Page |
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it Online |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1335 7C1335 CY7C1335-100AC
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| OCR Text |
...t sequence is controlled by the adv input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualifie... |
| Description |
32K X 32 CACHE SRAM, 5 ns, PQFP100
32K x 32 Synchronous-Pipelined Cache RAM(32K x 32 同步流水线式高速缓冲存储器 RAM) 32K的32同步流水线缓存内存（32K的32同步流水线式高速缓冲存储器的RAM
From old datasheet system
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| File Size |
277.35K /
15 Page |
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it Online |
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Cypress
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| Part No. |
CY7C1336 7C1336
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| OCR Text |
...led by the address advancement (adv) input. A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous Chip Enable input and an asynchronous Output Enable input provide easy control for bank selectio... |
| Description |
64K x 32 Synchronous Flow-Through 3.3V Cache RAM
From old datasheet system
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| File Size |
189.16K /
12 Page |
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it Online |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1337 7C1337
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| OCR Text |
...t sequence is controlled by the adv input. Byte write operations are qualified with the four Byte Write Select (BW[0-3]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are co... |
| Description |
32K x 32 Synchronous-Pipelined Cache RAM(32K x 32 同步流水线式高速缓冲存储器 RAM)
From old datasheet system
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| File Size |
320.45K /
17 Page |
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it Online |
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Cypress
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| Part No. |
CY7C1338 7C1338
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| OCR Text |
...led by the address advancement (adv) input. A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip enable input and an asynchronous output enable input provide easy control for bank selectio... |
| Description |
128K x 32 Synchronous-Flow-Through 3.3V Cache RAM
From old datasheet system
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| File Size |
271.46K /
16 Page |
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it Online |
Download Datasheet |
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