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Cypress
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| Part No. |
CY7C1303BV25-100BZXC CY7C1306BV25-100BZXC
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| OCR Text |
...w and flight time mismatching * Single multiplexed address input bus latches address inputs for both Read and Write ports * Separate Port Se...Byte Write Select 0, 1, 2 and 3 - active LOW. Sampled on the rising edge of the K and K clocks durin... |
| Description |
18-Mbit Burst of 2 Pipelined SRAM with QD(TM) Architecture
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| File Size |
246.26K /
19 Page |
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Cypress
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| Part No. |
CY7C1304DV25-100BZXC
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| OCR Text |
...w and flight time mismatching * Single multiplexed address input bus latches address inputs for both Read and Write ports * Separate Port Se...Byte Write Select 0 and 1, active LOW. Sampled on the rising edge of the K and K clocks during Write... |
| Description |
9-Mbit Burst of 4 Pipelined SRAM with QDR(TM) Architecture
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| File Size |
224.85K /
18 Page |
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it Online |
Download Datasheet |
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Cypress
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| Part No. |
CY7C1323BV25-100BZXC
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| OCR Text |
...d operations or K and K when in single clock mode. When Read access is deselected, Q[35:0] are automatically three-stated. Synchronous Load....Byte Write Select 0, 1, 2 and 3 - active LOW. Sampled on the rising edge of the K and K clocks durin... |
| Description |
18-Mbit 4-Word Burst SRAM with DDR-I Architecture
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| File Size |
259.39K /
18 Page |
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it Online |
Download Datasheet |
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Atmel
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| Part No. |
TSS463-AA
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| OCR Text |
...rator and Buffered Clock Output Single +5V Power Supply 0.8 m CMOS Technology SO16 Package
VAN Data Link Controller with Serial Interface...byte RAM and a register area divided into 11 control registers, 14 channel register sets and 128 byt... |
| Description |
VAN (ISO Standard 11519-3) datalink controller with serial interface.
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| File Size |
691.75K /
60 Page |
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it Online |
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Philips
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| Part No. |
TDA9885HN/V3 TDA9885T/V3 TDA9885TS/V3 TDA9886HN/V4 TDA9886T/V4
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| OCR Text |
single and multistandard alignment-free IF-PLL demodulators
Product specification Supersedes data of 2002 Mar 05 2003 Oct 02
Philips Se...byte Write format Subaddress Data byte for switching mode Data byte for adjust mode Data byte for da... |
| Description |
I2C-bus controlled single and multistandard alignment-free IF-PLL demodulators
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| File Size |
239.44K /
56 Page |
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it Online |
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Philips
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| Part No. |
TDA9884TS TDA9884TS/V1
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| OCR Text |
... SIF amplifier SIF-AGC detector Single reference QSS mixer AM demodulator FM demodulator and acquisition help Audio amplifier and mute time ...byte Write format Subaddress Data byte for switching mode Data byte for adjust mode Data byte for da... |
| Description |
I²C-bus controlled multistandard alignment-free IF-PLL for mobile reception
I2C-bus controlled multistandard alignment-free IF-PLL for mobile reception
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| File Size |
222.58K /
55 Page |
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it Online |
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Electronic Theatre Controls, Inc.
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| Part No. |
SMJ27C010A SMJ27C010A-12 SMJ27C010A-15 SMJ27C010A-20
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| OCR Text |
...URES
* Organized 131,072 x 8 * Single +5V 10% power supply * Operationally compatible with existing megabit EPROMs * Industry standard 32-p...byte verification to determine when the addressed byte has been successfully programmed. Up to ten 1... |
| Description |
UVEPROM
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| File Size |
131.52K /
11 Page |
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it Online |
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Price and Availability
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