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				PHILIPS[Philips Semiconductors]
Part No.	PCF8577C PCF8577CP PCF8577CT PCF8577CU_10
OCR Text	...-on reset Slave address I2C-bus protocol Display memory mapping CHARACTERISTICS OF THE I2C-BUS Bit transfer Start and stop conditions System...enabled for loading, if not the device ignores incoming data but remains active. The three least-sig...
Description	LCD direct/duplex driver with I2C-bus interface
File Size	174.96K / 28 Page	View it Online	Download Datasheet

				PHILIPS[Philips Semiconductors]
Part No.	PCF8593 PCF8593P PCF8593T PCF8593T/1
OCR Text	...nfiguration Acknowledge I2C-BUS PROTOCOL Addressing Clock/calendar READ/WRITE cycles I2C-BUS 10 11 12 13 14 14.1 14.1.1 14.1.2 14.1.3 15 16 ...enabled). The flags remain set until directly reset by a write operation. When the alarm is disabled...
Description	PCF8593; Low power clock/calendar From old datasheet system
File Size	128.52K / 28 Page	View it Online	Download Datasheet

				SIPEX[Sipex Corporation]
Part No.	SP5301 SP5301CN SP5301CY SP5301CY-L SP5301CY-L/TR SP5301CN-L SP5301CN-L/TR
OCR Text	...e for PC peripheral expansion s Protocol flexibility for mixed-mode isochronous data transfers and asynchronous messaging s Available in 14 ...enabled by the OE pin. If OE is asserted LOW, the driver is active and the D- and D+ pins drive USB ...
Description	Universal Serial Bus Transceiver
File Size	185.27K / 13 Page	View it Online	Download Datasheet

				ZILOG[Zilog, Inc.]
Part No.	Z53C80 Z53C8003PSC Z53C8003VSC Z53C80SCSI
OCR Text	... and Initiator Roles Meets SCSI Protocol as Defined in ANSI X3.131-1986 Standard Added "Glitch Eater" Enhancement to Minimize Bus Reflection...enabled, the SCSI Bus parity is checked at the beginning of the read cycle. This register is used du...
Description	SMALL COMPUTER SYSTEM INTERFACE (SCSI)
File Size	213.70K / 40 Page	View it Online	Download Datasheet

				ATMEL[ATMEL Corporation]
Part No.	AT88SC1608-09ET-00 AT88SC1608-09PT-00 AT88SC1608-10CI-00 AT88SC1608-10PI-00 AT88SC1608-10SI-00 AT88SC1608-10WI-00 AT88SC1608
OCR Text	...tapping - 64-bit Authentication Protocol (under exclusive patent license from ELVA) - Authentication Attempts Counter - Eight Sets of Two 24...enabled (WPE = "0"), the user is required to verify the write password to allow write operations in ...
Description	8 x 256 x 8 Secure Memory with Authentication
File Size	194.09K / 25 Page	View it Online	Download Datasheet

				Holt Integrated Circuits, Inc. HOLTIC[Holt Integrated Circuits]
Part No.	HI-6010 HI-6010C HI-6010CM-01 HI-6010CT HI-6010J HI-6010JT
OCR Text	...incoming data meet the standard protocol and the transmitter outputs a standard protocol stream. The HI-6010 provides flexible options for i...enabled RXRDY goes high normally Blocks RXRDY for one ARINC word Self test disabled Self test enable...
Description	ARINC 429 TRANSMITTER/RECEIVER FOR 8 BIT BUS 1 CHANNEL(S), SERIAL COMM CONTROLLER, CDIP28 128 MACROCELL 3.3 VOLT ISP CPLD - NOT RECOMMENDED for NEW DESIGN ARINC 429 Transmitter/Receiver for 8-Bit Bus
File Size	381.69K / 12 Page	View it Online	Download Datasheet

				Samsung Semiconductor Co., Ltd. SAMSUNG SEMICONDUCTOR CO. LTD. SAMSUNG[Samsung semiconductor] Samsung Electronic
Part No.	K7P401822M-H16 K7P401822M-H19 K7P401822M-H20 K7P403622M K7P403622M-H16 K7P403622M-H19 K7P403622M-H20 K7P401822B-HC16 K7P401822B-HC20 K7P401822B-HC25 K7P403622B-HC16 K7P403622B-HC20 K7P403622B-HC25
OCR Text	...iption Output Power Supply Read Protocol Mode Pins ( M1=VSS, M2=VDD ) Asynchronous Output Enable Synchronous Select JTAG Test Clock JTAG Tes...enabled by switching ZZ high. When the SRAM is in Power Down Mode, the outputs will go to a Hi-Z sta...
Description	128Kx36 & 256Kx18 Synchronous Pipelined SRAM 128K × 36 128Kx36 & 256Kx18 Synchronous Pipelined SRAM
File Size	239.13K / 12 Page	View it Online	Download Datasheet

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