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ICST[Integrated Circuit Systems]
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| Part No. |
ICS8702BYT ICS8702 ICS8702BY
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| OCR Text |
...ntial input signal (PECL, hstl, lvds) to LVCMOS levels without external bias networks Translates any single-ended input signal to LVCMOS le...lvpecl Levels DCM , hstl, lvds, SSTL Levels VDDI = VIN = 3.465V VDDI = VIN = 3.465V VDDI = 3.465, VI... |
| Description |
LOW SKEW ±1, ±2 CLOCK GENERATOR
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| File Size |
186.44K /
12 Page |
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ONSEMI[ON Semiconductor]
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| Part No. |
NB100LVEP91_06 NB100LVEP91 NB100LVEP91DW NB100LVEP91DWG NB100LVEP91DWR2 NB100LVEP91DWR2G NB100LVEP91MN NB100LVEP91MNG NB100LVEP91MNR2 NB100LVEP91MNR2G NB100LVEP9106
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| OCR Text |
...CL, LVTTL, LVCMOS, hstl, CML or lvds signals, and translates them to differential LVNECL output signals (-2.5 V / -3.3 V). To accomplish the...lvpecl, lvds, LVTTL, LVCMOS, CML, hstl Input lvpecl, lvds, LVTTL,LVCMOS, CML, hstl Input LVNECL Outp... |
| Description |
2.5 V/3.3 V Any Level Positive Input to −2.5 V/−3.3 V LVNECL Output Translator
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| File Size |
142.11K /
10 Page |
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IDT[Integrated Device Technology]
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| Part No. |
IDT5T9310NLI IDT5T9310 IDT5T9310NLI8
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| OCR Text |
lvds 1:10 CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
2.5V lvds 1:10 CLOCK BUFFER TERABUFFERTM II
FEATURES:
* * * * * * ...lvpecl (3.3V), CML, or lvds input interface Selectable differential inputs to ten lvds outputs Power... |
| Description |
2.5V lvds 1:10 CLOCK BUFFER TERABUFFER II
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| File Size |
88.04K /
12 Page |
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IDT[Integrated Device Technology]
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| Part No. |
IDT5T9316NLI IDT5T9316 IDT5T9316NLI8
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| OCR Text |
lvds 1:16 CLOCK BUFFER TERABUFFER II
INDUSTRIAL TEMPERATURE RANGE
2.5V lvds 1:16 CLOCK BUFFER TERABUFFERTM II
FEATURES:
* * * * * * ...lvpecl (3.3V), CML, or lvds input interface Selectable differential inputs to sixteen lvds outputs P... |
| Description |
2.5V lvds 1:16 CLOCK BUFFER TERABUFFER II
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| File Size |
92.92K /
12 Page |
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it Online |
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AMI[AMI SEMICONDUCTOR]
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| Part No. |
X2P998 X2P1148 X2P1346 X2P376 X2P528 X2P680
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| OCR Text |
... class 1 and 2, lvpecl (input), lvds I/O standards * 1.5V, 1.8V, 2.5V, and 3.3V capable I/O * True 3.3V tolerance with no external resistor necessary * Digital controlled impedance * Built-in DDR support * lvds data rates to 1Gbps * Up to 1... |
| Description |
0.15mm Structured ASIC
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| File Size |
930.24K /
14 Page |
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Altera, Corp.
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| Part No. |
EP20K400E
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| OCR Text |
...t co + t su ) up to 250 mhz ? lvds performance up to 840 mbits per channel ? direct connection from i/o pins to local interconnect provid...lvpecl data pins (in ep20k300e and larger devices) lvds and lvpecl signaling (in all bga and fin... |
| Description |
Programmable Logic Device Family 可编程逻辑器件系列
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| File Size |
593.38K /
117 Page |
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it Online |
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Price and Availability
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