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Freescale Semiconductor, Inc.
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| Part No. |
KMPC8349EZUAGDB
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| OCR Text |
... technology ? double data rate, ddr1/ddr2 sdram memory controller ? programmable timing supporting ddr1 and ddr2 sdram ? 32- or 64-bit data interface, up to 400 mhz data rate ? up to four physical banks (chip selects), each bank up to 1 gby... |
| Description |
32-BIT, 400 MHz, MICROPROCESSOR, PBGA672 35 X 35 MM, 1.50 MM HEIGHT, 1 MM PITCH, TBGA-672
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| File Size |
1,163.87K /
128 Page |
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it Online |
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Integrated Device Technology, Inc.
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| Part No. |
IDTCSPT857CPAI IDTCSPT857CPFI
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| OCR Text |
...r clock driver ? meets proposed ddr1-400 specification ? for all ddr1 speeds: pc1600 (ddr200), pc2100 (ddr266), pc2700 (ddr333), pc3200 (ddr400) ? along with sstv16857, sstvf16857, sstv16859, sstvm16859, sstvf16859, ddr1 register, provides ... |
| Description |
2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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| File Size |
140.09K /
15 Page |
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it Online |
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Integrated Device Technology, Inc.
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| Part No. |
ICS95V857YL-130 ICS95V857YG-130
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| OCR Text |
...er. meets or exceeds proposed ddr1-400 specifications covers all ddr1 speed grades switching characteristics: cycle - cycle jitter (>100mhz):<50ps output - output skew: <30ps output rise and fall time: 650ps - 950ps duty cycle: ... |
| Description |
PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 0.173 INCH, TSSOP-48
PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 0.240 INCH, TSSOP-48
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| File Size |
188.12K /
13 Page |
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it Online |
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Price and Availability
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