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MC3456 TC206B 180515 45DB321 N4948 R1500 KP110 BD6665FM
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  aligns Datasheet PDF File

For aligns Found Datasheets File :: 1369    Search Time::0.812ms    
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    AD5231BRU10 AD5231BRU10-REEL7 AD5231BRU50

Analog Devices
Part No. AD5231BRU10 AD5231BRU10-REEL7 AD5231BRU50
OCR Text ...POL = 1 MICROCONTROLLER COMMAND aligns THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK. Figure 2a. CPHA = 1 Timing Diagram CS CPHA = 0 t12 t1 t2 CLK CPOL = 0 t3 t5 t17 t13 t4 t8 t10 t11 t9 SDO MSB OUT ...
Description Nonvolatile Memory, 1024-Position Digital Potentiometers

File Size 393.70K  /  24 Page

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    ICS2402 ICS2402M ICS2402MLF ICS2402MLFT ICS2402MT

Integrated Circuit Systems
Part No. ICS2402 ICS2402M ICS2402MLF ICS2402MLFT ICS2402MT
OCR Text ... rising edge of the input clock aligns with the rising edges of both output clocks, giving the appearance of no delay through the device. The ICS2402 is ideal for synchronizing outputs in a large variety of systems, from personal computers ...
Description Multiplier and Zero Delay Buffer

File Size 82.30K  /  7 Page

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    Intersil
Part No. ISL5314 FN4901
OCR Text ...8 bits because the MSB (bit 47) aligns with the most significant address bit of the sine ROM and the ROM contains one cycle of a sinusoid. The MSB is weighted at 180 degrees. Full scale is 360 degrees minus 1 LSB and the phase then rolls ov...
Description CommLink Direct Digital Synthesizer
From old datasheet system

File Size 163.18K  /  16 Page

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    AD5328 AD5308 3601

Analog Devices
Part No. AD5328 AD5308 3601
OCR Text ...POL = 1 MICROCONTROLLER COMMAND aligns THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK. Figure 2a. CPHA = 1 Timing Diagram CS CPHA = 0 t12 t1 t2 CLK CPOL = 0 t3 t5 t17 t13 t4 t8 t10 t11 t9 SDO MSB OUT ...
Description 2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP
From old datasheet system

File Size 412.10K  /  24 Page

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    Cypress
Part No. CY7B952 7B952
OCR Text ... LOW, the Receive PLL no longer aligns to RIN, but instead aligns with the REFCLKx8 frequency. Also, the Link Fault Indicator (LFI) will transition LOW, and the recovered data outputs (RSER) will remain LOW regardless of the signal level on...
Description SST?SONET/SDH Serial Transceiver
From old datasheet system

File Size 132.92K  /  9 Page

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    VSC8113 VSC8113QB VSC8113QB1 VSC8113QB2

Vitesse Semiconductor Corporation
Part No. VSC8113 VSC8113QB VSC8113QB1 VSC8113QB2
OCR Text ...ch detects the SONET/SDH frame, aligns the received serial data on byte boundaries, and initiates a frame pulse on FP coincident with the byte aligned data. The frame recovery is initiated when OOF is held high which must occur at least 4 b...
Description ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation and Clock Recovery

File Size 272.90K  /  28 Page

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    K4D28163HD K4D28163HD-TC36 K4D28163HD-TC40 K4D28163HD-TC50 K4D28163HD-TC60

Samsung Semiconductor Co., Ltd.
SAMSUNG SEMICONDUCTOR CO. LTD.
SAMSUNG[Samsung semiconductor]
Samsung Electronic
Part No. K4D28163HD K4D28163HD-TC36 K4D28163HD-TC40 K4D28163HD-TC50 K4D28163HD-TC60
OCR Text ...both edges of Data strobe * DLL aligns DQ and DQS transitions with Clock transition * Edge aligned data & data strobe output * Center aligned data & data strobe input * DM for write masking only * Auto & Self refresh * 32ms refresh period (...
Description 128Mbit DDR SDRAM 128Mbit DDR SDRAM

File Size 119.75K  /  16 Page

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