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  time-slot Datasheet PDF File

For time-slot Found Datasheets File :: 4619    Search Time::1.969ms    
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    Tripp Lite. All Rights ...
Part No. SUINT2000XLCD
OCR Text ...atures highlights zero transfer time suitable for advanced network applications l 2% output voltage regulation in online, double-conversion ...slot for snmp network interface and relay card for remote monitoring and control options l compatibl...
Description SmartOnline 230V 2kVA 1800W On-Line Double-Conversion UPS, Tower, Extended Run, Network Card Options, LCD, USB, DB9

File Size 172.98K  /  6 Page

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    YTD439

List of Unclassifed Manufacturers
ETC
Part No. YTD439
OCR Text ...criber line interface (two-wire time compression multiplexing operation) and the user-network interface (digital four-wire time division ful...slot 0 Time slot 1 Time slot 2 Time slot 3 Time slot 4 Time slot n-1 Time slot n n:7 (Min.) - 31 (Ma...
Description ISDN BRI controller for Terminal Equipment with built-in DSU

File Size 177.86K  /  15 Page

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    Tripp Lite. All Rights ...
Part No. SUINT1000XLCD
OCR Text ...ntrol. highlights zero transfer time suitable for advanced network applications l 2% output voltage regulation in online, double-conversion ...slot for snmp network interface and relay card for remote monitoring and control options l compatibl...
Description SmartOnline 230V 1kVA 900W On-Line Double-Conversion UPS, Tower, Extended Run, Network Card Options, LCD, USB, DB9

File Size 172.53K  /  6 Page

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    IDT72V71623 IDT72V71623BC IDT72V71623DA IDT72V71623BC8

IDT[Integrated Device Technology]
Part No. IDT72V71623 IDT72V71623BC IDT72V71623DA IDT72V71623BC8
OCR Text TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 2,048 x 2,048 FEATURES: * * * * * * * * * * * * IDT72V71623 Up to 16 serial input and output streams Maximum 2,048 x 2,048 channel non-blocking switching Accepts data streams a...
Description 2K x 2K TSI, 16 I/O at 2/4/8 or 16Mbps, Rate-Matching, 3.3V
3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 2,048 x 2,048

File Size 198.53K  /  28 Page

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    IDT72V71643 IDT72V71643BC IDT72V71643DA IDT72V71643BC8

IDT[Integrated Device Technology]
Part No. IDT72V71643 IDT72V71643BC IDT72V71643DA IDT72V71643BC8
OCR Text TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING 4,096 x 4,096 FEATURES: * * * * * * * * * * * * * * * IDT72V71643 Up to 32 serial input and output streams Maximum 4,096 x 4,096 channel non-blocking switching Accepts data str...
Description 4K x 4K TSI, 32 I/O at 2/4/8 or 16Mbps, Rate-Matching, 3.3V
3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH WITH RATE MATCHING
TSI-TDM Switches

File Size 214.95K  /  30 Page

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    ST Microelectronics
Part No. M34116 M34116B1
OCR Text ... initialization routine takes 2 time frames starting from the rising edge of reset. during this initialization time, all data bus and pcm ou...slot with respect to the output channel involved in the conference in overflow. example: if output c...
Description PCM CONFERENCE CALL AND TONE GENERATION CIRCUIT

File Size 376.52K  /  23 Page

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    Atmel Corp.
Atmel, Corp.
Part No. AT91SAM9260-QU AT91SAM9260-CJ ATMELCORP.-AT91SAM9260
OCR Text ... Timer, Watchdog Timer and Real-time Timer Reset Controller (RSTC) - Based on a Power-on Reset Cell, Reset Source Identification and Reset O...slot MultiMedia Card Interface (MCI) - SDCard/SDIO and MultiMediaCardTM Compliant - Automatic Protoc...
Description AT91 ARM Thumb Microcontrollers 32-BIT, FLASH, 210 MHz, RISC MICROCONTROLLER, PBGA217
AT91 ARM Thumb Microcontrollers 32-BIT, FLASH, 210 MHz, RISC MICROCONTROLLER, PQFP208

File Size 567.91K  /  45 Page

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    MT9076

Mitel Networks Corporation
Part No. MT9076
OCR Text ...gnificant nibbles of each STBUS time slot are valid and the least significant nibbles of each ST-BUS time slot are tristated when control bit MSN (page 01H, address 1AH, bit 1) is set to 1. If MSN=0, the position of the valid and tristated ...
Description T1/E1/J1 3.3V Single Chip Transceiver(T1/E1/J1 3.3V 单片收发

File Size 492.72K  /  162 Page

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    MT9074

Mitel Networks Corporation
Part No. MT9074
OCR Text ...nificant nibbles of each ST-BUS time slot are valid and the least significant nibbles of each ST-BUS time slot are tristated when control bit MSN (page 01H, address 1AH, bit 1) is set to 1. If MSN=0, the position of the valid and tristated ...
Description T1/E1/J1 Single Chip Transceiver(T1/E1/J1单片收发

File Size 409.91K  /  120 Page

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