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ONSEMI[ON Semiconductor]
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| Part No. |
NB7N017M06 NB7N017MMNR2G NB7N017M NB7N017MMN NB7N017MMNG NB7N017MMNR2
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| OCR Text |
...gle-Ended Control Pins CMOS and pecl/NECL Compatible Counter Programmed Using One of Two Single-Ended Words, Pa[0:7] and Pb[0:7], Stored in ...lvds, LVTTL Input ECL, cml, LVCMOS, lvds, LVTTL Input CMOS, ECL Input Default State - - Low Single/D... |
| Description |
3.3V SiGe 8−Bit Dual Modulus Programmable Divider/Prescaler with cml Outputs
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| File Size |
136.15K /
19 Page |
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ONSEMI[ON Semiconductor]
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| Part No. |
NBSG16MNR2 NBSG16MN NBSG16BAR2 NBSG16BAEVB NBSG16BA NBSG16
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| OCR Text |
...and accept NECL (Negative ECL), pecl (Positive ECL), HSTL, LVTTL, LVCMOS, cml, or lvds. Outputs are RSECL (Reduced Swing ECL), 400 mV. The VBB and VMM pins are internally generated voltage supplies available to this device only. The VBB is ... |
| Description |
2.5 V/3.3 V SiGe Differential Receiver/Driver with RSECL Outputs
From old datasheet system
2.5V/3.3V SiGe Differential Receiver/Driver with RSECLOutputs
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| File Size |
104.60K /
10 Page |
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ONSEMI[ON Semiconductor]
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| Part No. |
NBSG86A NBSG86AMNR2 NBSG86AMN NBSG86ABAR2 NBSG86ABA
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| OCR Text |
...and accept NECL (Negative ECL), pecl (Positive ECL), LVCMOS/LVTTL, cml, or lvds. The OLS input is used to program the peak-to-peak output amplitude between 0 and 800 mV in five discrete steps. The NBSG86A employs input default circuitry so ... |
| Description |
2.5V/3.3V SiGe Differential Smart Gate with Output Level Select
2.5V/3.3VSiGe Differential Smart Gate with Output Level Select
Evaluation Board Manual
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| File Size |
113.78K /
14 Page |
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MAXIM - Dallas Semiconductor
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| Part No. |
MAX3890
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| OCR Text |
...ferenced emitter-coupled logic (pecl) serial data and clock outputs. a fully integrated phase- locked loop (pll) synthesizes an internal 2.5...lvds parallel clock and data inputs additional high-speed output for system loopback testing max389... |
| Description |
3.3V, 2.5Gbps, SDH/SONET 16:1 Serializer with Clock Synthesis and lvds Inputs
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| File Size |
261.57K /
12 Page |
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MAXIM INTEGRATED PRODUCTS INC
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| Part No. |
MAX3950EGK-TD
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| OCR Text |
...- 1.0: interfacing between cml, pecl, and lvds . pin name function 15 pclk+ positive parallel clock output, 622.08mhz, lvds. 19, 21, 23, 27, 29, 38, 40, 44, 46, 48, 56, 58, 62, 64, 66, 3 pd0- to pd15- negative parallel data output, 622.08mb... |
| Description |
3.3V, 10.7Gbps 1:16 Deserializer with lvds Outputs
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| File Size |
428.97K /
11 Page |
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it Online |
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Price and Availability
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