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Maxim
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| Part No. |
MAX3861
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| OCR Text |
... Bandwidth Low-Frequency Cutoff deterministic Jitter Output Signal Monitor Voltage Output Signal Monitor Linearity SC Input Range AGC Loop Constant VOSM SYMBOL VOUT VOUT BW CONDITIONS RL = 50 to VCC (Note 6) VSC = 0 VSC = 2V At minimum gain... |
| Description |
2.7Gbps Post Amp with Automatic Gain Control
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| File Size |
720.50K /
11 Page |
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Maxim Integrated Products, Inc.
MAXIM - Dallas Semiconductor
MAXIM[Maxim Integrated Products]
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| Part No. |
MAX9311 MAX9313 MAX9313EHJ MAX9311ECJ MAX9311EGJ MAX9311EHJ MAX9313ECJ MAX9313EGJ
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| OCR Text |
...d Random Jitter (Note 10) Added deterministic Jitter (Note 10) SYMBOL CONDITIONS tPLHD, tPHLD -40C MIN 220 TYP 321 MAX 380 MIN 220 +25C TYP 312 MA 410 MIN 260 +85C TYP 322 MAX 400 UNITS
Figure 2
ps
tSKOO
12
46
12
46
... |
| Description |
Quadruple 2-Input Positive-NAND Gates 14-CDIP -55 to 125 1:10差分LVPECL/LVECL/HSTL时钟和数据驱动器
1:10 Differential LVPECL/LVECL/HSTL Clock and Data Drivers 9313 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
Quadruple 2-Input Positive-NAND Gates 20-LCCC -55 to 125 9311 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
1:10 Differential LVPECL/ LVECL/HSTL Clock and Data Drivers
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| File Size |
366.43K /
12 Page |
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it Online |
Download Datasheet |
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XILINX INC
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| Part No. |
XCR3032A DS039 XCR3032A-6VQ44C
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| OCR Text |
...ns and all macrocells are fixed deterministic timing model that is extremely simple to use Up to six clocks available Programmable clock polarity at every macrocell 3.3V, In-System Programmable (ISP) using a JTAG interface - On-chip supervo... |
| Description |
EE PLD, 6 ns, PQFP44
From old datasheet system
Product Specification
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| File Size |
297.55K /
16 Page |
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it Online |
Download Datasheet |
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XILINX INC
Xilinx, Inc.
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| Part No. |
XCR3032C DS040 XCR3032C-12VQ44C
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| OCR Text |
...ns and all macrocells are fixed deterministic timing model that is extremely simple to use Up to six clocks available Programmable clock polarity at every macrocell 3.3V, In-System Programmable (ISP) using a JTAG interface - On-chip supervo... |
| Description |
EE PLD, 12 ns, PQFP44
32 Macrocell CPLD with Enhanced Clocking(带增强时钟控制的32宏单元复杂可编程逻辑器件) 32宏单元CPLD增强型时钟（带增强时钟控制的32个宏单元复杂可编程逻辑器件
From old datasheet system
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| File Size |
297.73K /
16 Page |
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it Online |
Download Datasheet |
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