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Cypress Semiconductor, Corp.
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| Part No. |
CY7C1352-133AI
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| OCR Text |
...tive low. qualified with we to conduct writes to the sram. sampled on the rising edge of clk. bws 0 controls dq [7:0] and dp 0 , bws 1 controls dq [15:8] and dp 1 . see write cycle description table for details. 88 we input- synchron... |
| Description |
x18 Fast Synchronous SRAM x18快速同步SRAM
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| File Size |
194.23K /
13 Page |
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it Online |
Download Datasheet
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1353G-117AXC
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| OCR Text |
...e low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted lo... |
| Description |
4-Mbit (256K x 18) Flow-through SRAM with NoBLArchitecture 4兆位56 × 18）流通过总线延迟⑩建筑的SRAM
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| File Size |
217.30K /
13 Page |
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it Online |
Download Datasheet |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1345 7C1345
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| OCR Text |
...tive LOW. Qualified with BWE to conduct byte writes. Sampled on the rising edge. BW0 controls DQ [7:0] and DP0, BW1 controls DQ[15:8] and DP1, BW2 controls DQ[23:16] and DP2, and BW3 controls DQ [31:24] and DP3. See Write Cycle Description ... |
| Description |
128K x 36 Synchronous Flow-Through 3.3V Cache RAM(3.3V 128K x 36 同步流通式高速缓冲RAM) 128K的36同步流动，通过3.3V的高速缓存内存（3.3 128K的36同步流通式高速缓冲内存）
From old datasheet system
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| File Size |
272.33K /
16 Page |
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it Online |
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