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For protocol-enabled Found Datasheets File :: 4251 Search Time::3.734ms
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				MITEL[Mitel Networks Corporation]
Part No.	MT8931C-1 MT8931CE MT8931CP MT8931C MT8931CC
OCR Text	...ded on the SNIC for link access protocol handling via the D-channel. Depacketized data is passed to and from the transceiver via the micropr...enabled or disabled. Both, one and two byte address recognition is supported by the SNIC. A transpar...
Description	CMOS ST-BUS⑩ FAMILY Subscriber Network Interface Circuit Preliminary Information CMOS ST-BUS FAMILY Subscriber Network Interface Circuit
File Size	308.10K / 40 Page	View it Online	Download Datasheet

				Mitel Networks Corporation
Part No.	MT8931C MT8931CC
OCR Text	...ded on the SNIC for link access protocol handling via the D-channel. Depacketized data is passed to and from the transceiver via the micropr...enabled or disabled. Preliminary Information Both, one and two byte address recognition is suppo...
Description	CMOS ST-BUS FAMILY Subscriber Network Interface Circuit Preliminary Information
File Size	568.13K / 34 Page	View it Online	Download Datasheet

				Mitel Semiconductor MITEL[Mitel Networks Corporation]
Part No.	MT8952B-1 MT8952BE MT8952BP MT8952BS
OCR Text	Protocol Controller Features * * * * * * * * Formats data as per X.25 (CCITT) level-2 standards Go-Ahead sequence generation and detecti...enabled and when HIGH, CDSTo is in high impedance state. If the Protocol Controller is in the Intern...
Description	ISO-CMOS ST-BUS FAMILY HDLC Protocol Controller ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller
File Size	169.67K / 27 Page	View it Online	Download Datasheet

				Mitel Semiconductor MITEL[Mitel Networks Corporation]
Part No.	MT8952 MT8952B MT8952BC MT8952BS MT8952BE MT8952BP
OCR Text	Protocol Controller Features * * * * * * * * Formats data as per X.25 (CCITT) level-2 standards Go-Ahead sequence generation and detecti...enabled and when HIGH, CDSTo is in high impedance state. If the Protocol Controller is in the Intern...
Description	ISO-CMOS ST-BUS FAMILY HDLC Protocol Controller ISO-CMOS ST-BUS⑩ FAMILY HDLC Protocol Controller
File Size	160.74K / 22 Page	View it Online	Download Datasheet

				TOKO, Inc. STMicroelectronics N.V. Electronic Theatre Controls, Inc. XICOR[Xicor Inc.]
Part No.	X24645 X24645P X24645P-2.7 X24645PI X24645PI-2.7 X24645PM X24645PM-2.7 X24645S X24645S-2.7 X24645S8 X24645S8-2.7 X24645S8I X24645S8I-2.7 X24645S8M X24645S8M-2.7 X24645SI X24645SI-2.7 X24645SM X24645SM-2.7 X24645V X24645V-2.7 X24645VI X24645VI-2.7 X24645VM X24645VM-2.7
OCR Text	...a serial interface and software protocol allowing operation on a simple two wire bus. Two device select inputs (S1, S2) allow up to four dev...enabled, and nonvolatile writes are disabled to the selected blocks as well as the write protect reg...
Description	Voltage Regulator IC; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes 先进2线串行e2座门锁TM保护胎膜早破 Isolated Flyback Switching Regulator with 9V Output 隔离反激式开关稳9V输出 IC SW REG STEP-UP 1.4A SOT23-5 IC STEP-UP SW REG 1.4A 10-MLPD Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection
File Size	81.59K / 18 Page	View it Online	Download Datasheet

				XICOR[Xicor Inc.]
Part No.	X25045 X25045P X25045P-2.7 X25045PI X25045PI-2.7 X25045S X25045S-2.7 X25045SI X25045SI-2.7 X25045V X25045V-2.7 X25045VI X25045VI-2.7 X25043 X25043P X25043P-2.7 X25043PI X25043PI-2.7 X25043S X25043S-2.7 X25043SI X25043SI-2.7 X25043V X25043V-2.7 X25043VI X25043VI-2.7
OCR Text	...al Interface (SPI) and software protocol allowing operation on a simple three-wire bus. The X25043/45 utilizes Xicor's proprietary Direct Wr...enabled and CS remains either HIGH or LOW longer than the Watchdog time-out period. A falling edge o...
Description	XTAL MTL T/H HC49/U Programmable Watchdog Supervisory E2PROM
File Size	90.75K / 15 Page	View it Online	Download Datasheet

				PHILIPS[Philips Semiconductors]
Part No.	TZA1020A TZA1020 TZA1020HP TZA1020HP_A TZA1020HP/A
OCR Text	...ot position measurement I2C-BUS PROTOCOL Addressing and data bytes Write mode Read mode Control byte subaddress 00 Control byte subaddress 0...enabled/disabled integrator capacitor for alpha measurement central aperture high-frequency current ...
Description	Pre-amplifiers for CD-RW systems
File Size	144.59K / 36 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICS9179-03 ICS9179YG-03-T AV9179F-03-T ICS9179F-03-T
OCR Text	...lave-receiver device in the I2C protocol. It will allow read-back of the registers. See configuration map for register functions. The I2C sp...Enabled; 0 = Disabled, outputs held low Note: PWD = Power-Up Default Byte 1: OUTPUT Clock Registe...
Description	Low Skew Fan Out Buffers Clock Buffer
File Size	295.47K / 10 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICS9179-06 ICS9179F-06
OCR Text	...upport Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) ...Enabled; 0 = Disabled, outputs held low Notes: 1 = Enabled; 0 = Disabled, outputs held low Not...
Description	Zero Delay Buffers
File Size	459.54K / 8 Page	View it Online	Download Datasheet

				ICST[Integrated Circuit Systems]
Part No.	ICS9179-12 ICS9179M-12 AV9179F-12 ICS9179F-12 AV9179M-12
OCR Text	...lave-receiver device in the I2C protocol. It will allow read-back of the registers. See configuration map for register functions. The I 2 C ...Enabled; 0 = Disabled, outputs held low Note: PWD = Power-Up Default ICS9279-12 Power Consumption...
Description	High-Performance Impact-X<TM> PAL(R) Circuits 28-PLCC 0 to 75 3 DIMM Buffer 3dimm buffer
File Size	276.65K / 9 Page	View it Online	Download Datasheet

For protocol-enabled Found Datasheets File :: 4251 Search Time::3.734ms
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