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M/A-COM Technology Solu...
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| Part No. |
M21001 M21001G-12 M21001-12
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| OCR Text |
...upled input to cm l, lvds, and lvpecl. the outputs can also be dc-coupled to cml and lvds . frequency acquisition is accomplished with an external referenc e clock. the built-in frequency synthesizer allows multi-rate opera tion, while op... |
| Description |
Quad Multi-Rate CDR
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| File Size |
766.96K /
73 Page |
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Download Datasheet
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ICS
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| Part No. |
ICS854210
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| OCR Text |
...S bank outputs * 2 differential lvpecl clock input pairs * PCLKx, nPCLKx pairs can accept the following differential input levels: lvpecl, lvds, cml, SSTL * Maximum output frequency: 3.2GHz * Translates any single ended input signal to lvds... |
| Description |
Low Skew, Dual, 1-to-5, Differential-to-lvds Fanout Buffer
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| File Size |
134.64K /
10 Page |
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it Online |
Download Datasheet |
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ON Semiconductor
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| Part No. |
NB4N527S
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| OCR Text |
...ting anylevel tm input signal (lvpecl, cml, hstl, lvds, or lvttl/lvcmos) to lvds. depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signa... |
| Description |
Translator, 3.3 V, 2.5 Gb/s Dual AnyLevel™ to lvds Receiver/Driver/Buffer, with Internal Termination
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| File Size |
167.06K /
10 Page |
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it Online |
Download Datasheet |
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Price and Availability
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