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  divider pll Datasheet PDF File

For divider pll Found Datasheets File :: 5958    Search Time::7.281ms    
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    IMIZ9972BA IMIZ9972BAT IMIZ9972 Z9972

CYPRESS[Cypress Semiconductor]
CYPRESS SEMICONDUCTOR CORP
Part No. IMIZ9972BA IMIZ9972BAT IMIZ9972 Z9972
OCR Text ...FB_IN for normal operation. The divider ratio for this output is set by FB_SEL(0:2). See Table 1. A bypass delay capacitor at this output wi...pll. pll Enable Input. When asserted HIGH, pll is enabled. And when LOW, the phase-lock loop (pll) i...
Description Output frequency up to 125 MHz
3.3V, 125-MHz, Multi-Output Zero Delay Buffer
3.3V/ 125-MHz/ Multi-Output Zero Delay Buffer

File Size 86.56K  /  9 Page

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    AD9520-5 AD9520-5_PCBZ AD9520-5BCPZ AD9520-5BCPZ-REEL7

Analog Devices
Part No. AD9520-5 AD9520-5_PCBZ AD9520-5BCPZ AD9520-5BCPZ-REEL7
OCR Text ...s Each group of 3 has a 1-to-32 divider with phase delay Additive output jitter as low as 225 fs rms Channel-to-channel skew grouped outputs...pll REFIN SWITCHOVER AND MONITOR REF1 STATUS MONITOR CLK CLK divider AND MUXES ...
Description 12 LVPECL/24 CMOS Output Clock Generator

File Size 794.79K  /  80 Page

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    AD9520-4 AD9520-4_PCBZ AD9520-4BCPZ AD9520-4BCPZ-REEL7

Analog Devices
Part No. AD9520-4 AD9520-4_PCBZ AD9520-4BCPZ AD9520-4BCPZ-REEL7
OCR Text ...s Each group of 4 has a 1-to-32 divider with phase delay Additive output jitter as low as 225 fS rms Channel-to-channel skew grouped outputs...pll VCO CLK divider AND MUXs ZERO DELAY LVPECL/ CMOS DIV/ OUT0 OUT1 OUT2 OUT3 OUT4...
Description 12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO

File Size 923.33K  /  84 Page

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    AD9520-3 AD9520-3_PCBZ AD9520-3BCPZ AD9520-3BCPZ-REEL7

Analog Devices
Part No. AD9520-3 AD9520-3_PCBZ AD9520-3BCPZ AD9520-3BCPZ-REEL7
OCR Text ...s Each group of 3 has a 1-to-32 divider with phase delay Additive output jitter as low as 225 fs rms Channel-to-channel skew grouped outputs...pll VCO CLK divider AND MUXES ZERO DELAY LVPECL/ CMOS DIV/ OUT0 OUT1 OUT2 OUT3 OUT...
Description 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2 GHz VCO

File Size 924.98K  /  84 Page

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    AD9520-2 AD9520-2_PCBZ AD9520-2BCPZ AD9520-2BCPZ-REEL7

Analog Devices
Part No. AD9520-2 AD9520-2_PCBZ AD9520-2BCPZ AD9520-2BCPZ-REEL7
OCR Text ...s Each group of 3 has a 1-to-32 divider with phase delay Additive output jitter as low as 225 fs rms Channel-to-channel skew grouped outputs...pll VCO CLK divider AND MUXES ZERO DELAY LVPECL/ CMOS DIV/ OUT0 OUT1 OUT2 OUT3 OUT...
Description 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO

File Size 909.63K  /  84 Page

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    AD9520-1 AD9520-1_PCBZ AD9520-1BCPZ AD9520-1BCPZ-REEL7

Analog Devices
Part No. AD9520-1 AD9520-1_PCBZ AD9520-1BCPZ AD9520-1BCPZ-REEL7
OCR Text ...s Each group of 3 has a 1-to-32 divider with phase delay Additive output jitter as low as 225 fs rms Channel-to-channel skew grouped outputs...pll VCO CLK divider AND MUXES ZERO DELAY LVPECL/ CMOS DIV/ OUT0 OUT1 OUT2 OUT3 OUT...
Description 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.5 GHz VCO

File Size 913.03K  /  84 Page

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    AD9520-0 AD9520-0_PCBZ AD9520-0BCPZ AD9520-0BCPZ-REEL7

Analog Devices
Part No. AD9520-0 AD9520-0_PCBZ AD9520-0BCPZ AD9520-0BCPZ-REEL7
OCR Text ...s Each group of 3 has a 1-to-32 divider with phase delay Additive output jitter as low as 225 fs rms Channel-to-channel skew grouped outputs...pll VCO CLK divider AND MUXES ZERO DELAY LVPECL/ CMOS DIV/ OUT0 OUT1 OUT2 OUT3 OUT...
Description 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO

File Size 895.88K  /  84 Page

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    LC72137M LC72137

SANYO[Sanyo Semicon Device]
Part No. LC72137M LC72137
OCR Text ...gh-speed programmable frequency divider -- FMIN: 10 to 160 MHz.....Pulse swallower (divide-by-two prescaler built in) -- AMIN: 2 to 40 MHz.....pll block stopped (pll inhibit), Xtal oscillator operating (Xtal = 75 kHz) VDD: pll block stopped, X...
Description pll Frequency Synthesizer for Electronic Tuning

File Size 348.32K  /  23 Page

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    ACS8947T

Semtech Corporation
Part No. ACS8947T
OCR Text ......................... 10 Input divider DIVIP .................................................................................................pll Configuration .....................................................................................
Description Jitter Attenuating, Multiplying Phase-Locked Loop with Automatic Input Switch and Data Resynchronization Path

File Size 1,705.95K  /  30 Page

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    HMC837LP6CE

Analog Devices
Part No. HMC837LP6CE
OCR Text ...ump, a low noise reference path divider and a fractional divider. the fractional synthesizer features an advanced delta-sigma modulator desi...pll input 2050 2300 mhz rf output frequency at f vco /2 1025 1150 mhz rf output frequency at f vco 2...
Description FRACTIONAL-N pll WITH INTEGRATED VCO

File Size 771.89K  /  12 Page

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