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TI store
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| Part No. |
DS90LV049HMT/NOPB
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| OCR Text |
...in the differential propagation delays between the positive going edge and the negative going edge of the same driver channel. (5) t skd2 or differential channel-to-channel skew is defined as the magnitude difference in the differential pro... |
| Description |
<font color=red>[Old version datasheet]</font> High Temperature 3V LVDS Dual Line Driver and Receiver Pair
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| File Size |
948.98K /
19 Page |
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List of Unclassifed Manufacturers
ETC
QuickLogic Corp.
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| Part No. |
QL2003 QL2003_DS QL2003-0PF100C QL2003-0PF100I QL2003-0PF144C QL2003-0PF144I QL2003-0PL84I QL2003-1PF100I QL2003-1PL84C QL2003-2PF144C QL2003-2PL84C QL2003-2PL84I QL2003-XPF144I QL2003-XPL84C QL2003-1PF100C QL2003-1PF144I QL2003-1PL84I QL2003-2PF100I QL2003-XPF100C QL2003-0PL84C QL2003-XPF144C QL2003-1PF144C QL2003-2PF100C QL2003-2PF144I QL2003-XPF100I QL2003-XPL84I
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| OCR Text |
...
- Input + logic cell + output delays under 6 ns - Datapath speeds exceeding 225 MHz - Counter speeds over 200 MHz
3-6
QL2003
PINOUT DIAGRAM
84-PIN PLCC
3
pASIC 2
3-7
QL2003
PINOUT DIAGRAMS PIN # 76 PIN # 1 100-PIN TQF... |
| Description |
3.3V and 5.0V pASIC2 FPGA combining speed, density, low cost and flexibility.
3.3V and 5.0V pASICò 2 FPGA
From old datasheet system
3.3V AND 5.0V PASIC-R 2 FPGA COMBINING SPEED, DENSITY, LOW COST AND FLEXIBILITY
3.3V and 5.0V pASIC 2 FPGA Combining Speed, Density, Low Cost and Flexibility(高速，高可用密度，低成本、可适应性强.3V.0V pASIC 2系列场可编程逻辑器件)
FPGA, 192 CLBS, 5000 GATES, 200 MHz, PQCC84
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| File Size |
329.53K /
10 Page |
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it Online |
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ON Semi
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| Part No. |
MC100EP195_D ON0491
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| OCR Text |
...that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80 ps. These two elements provide the EP195 with a digitally-selectable resolution of approximately 20 ps. The required device delay is selected... |
| Description |
PROGRAMMABLE DELAY CHIP
From old datasheet system
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| File Size |
86.63K /
5 Page |
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it Online |
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SGS Thomson Microelectronics
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| Part No. |
74LCX157MTR
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| OCR Text |
...at 24 ma n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 2.0v to 3.6v (1.5v data retention) n pin and function compatible with 74 series 157 n latch-up performance exceeds 500ma (jesd 17) n esd performan... |
| Description |
LOW VOLTAGE CMOS QUAD 2 CHANNEL MULTIPLEXER WITH 5V TOLERANT INPUTS
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| File Size |
65.51K /
9 Page |
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it Online |
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Price and Availability
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