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FREESCALE SEMICONDUCTOR INC
Motorola, Inc
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| Part No. |
MCM63P837ZP200R MCM63P919ZP200R MCM63P837ZP200 MCM63P919ZP200 MCM63P837ZP225 MCM63P919ZP225 MCM63P837ZP225R MCM63P919ZP225R MCM63P837TQ166R MCM63P837TQ200 MCM63P837TQ200R MCM63P837TQ225 MCM63P837TQ225R MCM63P837ZP166 MCM63P837ZP166R MCM63P919TQ225 MCM63P919TQ200 MCM63P919TQ200R MCM63P919TQ225R MCM63P919TQ166R MCM63P919ZP166R
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| OCR Text |
...e being used, tie this pin low. Boundary Scan Pin, Test Clock: If boundary scan is not used, TCK must be tied to VDD or VSS. Boundary Scan Pin, Test Data In. Boundary Scan Pin, Test Data Out. Boundary Scan Pin, Test Mode Select. Boundary Sc... |
| Description |
512K X 18 CACHE SRAM, 3 ns, PBGA119
512K X 18 CACHE SRAM, 2.6 ns, PBGA119
256K x 36 and 512K x 18 Bit Pipelined BurstRAM Synchronous Fast Static RAM
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| File Size |
722.10K /
30 Page |
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Download Datasheet
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Xilinx, Inc.
XILINX INC
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| Part No. |
XC2S100-5FG256C XC2S100-5FG256I XC2S100 XC2S15-5VQG100C XC2S15-5VQG100I XC2S50-5CS144C XC2S50-5CS144I XC2S50-5CSG144I XC2S50-5FG256C XC2S50-5FG256I XC2S50-5FG456C XC2S50-5FG456I XC2S50-5PQ208C XC2S50-5PQ208I XC2S50-5TQ144C XC2S50-5TQ144I XC2S150 XC2S200 XC2S100-5CS144C XC2S100-5FG456C XC2S100-5FG456I XC2S100-5PQ208C XC2S100-5PQ208I XC2S100-5TQ144C XC2S50 XC2S30-5CS144C XC2S30-5CS144I XC2S30-5CSG144I XC2S30-5FG256C XC2S30-5FG256I XC2S30-5FG456C XC2S30-5FG456I XC2S30-5FGG256C XC2S30-5FGG256I XC2S30-5PQ208C XC2S30-5PQ208I XC2S30-5PQG208C XC2S30-5PQG208I XC2S30-5TQ144C XC2S30-5TQ144I XC2S15-5TQ144C XC2S15-5TQG144I XC2S15-6VQ100C XC2S30-6VQ100C XC2S50-6VQ100C XC2S100-6VQ100C XC2S150-6VQ100C XC2S200-6VQ100C XC2S100-6PQG208C XC2S15-6CS144C XC2S15-6CS144I XC2S15-6CSG144I XC2S50-6CS144C XC2S150-6CS144C XC2S30-6CS144C XC2S100-6CS144C XC2S200-6CS144C XC2S200-5PQ208C XC2S200-5VQ100C XC2S100-5VQ100C XC2S100-6PQG208I XC2S200-6PQG208C XC2S200-6PQ208I XC2S100-6PQ208I XC2S200-6TQ144C XC2S100-6VQ100I XC2S100-6VQG100I XC2S200-6VQG100C XC2S100-6VQG100C XC2S200-6VQ100I XC2S200-6PQ208C XC2S200-5TQ144C XC2S100-6TQ144C XC2S100-6PQ208C XC2S30-6FG256C XC2S30-6FG456I XC2S30-6TQ144C XC2S30-6FGG256C XC2S30-6FG
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| OCR Text |
...stribution: Delay-Locked Loop - Boundary Scan Development System Configuration - Configuration Timing Design Considerations
Module 4: Pinout Tables
DS001-4 (v2.8) June 13, 2008 * * Pin Definitions Pinout Tables
* * *
IMPORTANT NOT... |
| Description |
Spartan-II FPGA Family Data Sheet
30000 SYSTEM GATE 2.5 VOLT LOGIC CELL AR - NOT RECOMMENDED for NEW DESIGN FPGA, 216 CLBS, 30000 GATES, 263 MHz, PQFP144
100000 SYSTEM GATE 2.5 VOLT LOGIC CELL A - NOT RECOMMENDED for NEW DESIGN FPGA, 600 CLBS, 100000 GATES, 263 MHz, PBGA256
150000 SYSTEM GATE 2.5 VOLT LOGIC CELL A - NOT RECOMMENDED for NEW DESIGN FPGA, 864 CLBS, 150000 GATES, 263 MHz, PBGA456
200000 SYSTEM GATE 2.5 VOLT LOGIC CELL A - NOT RECOMMENDED for NEW DESIGN FPGA, 1176 CLBS, 200000 GATES, 263 MHz, PBGA256
200000 SYSTEM GATE 2.5 VOLT LOGIC CELL A - NOT RECOMMENDED for NEW DESIGN FPGA, 1176 CLBS, 200000 GATES, 263 MHz, PBGA456
100000 SYSTEM GATE 2.5 VOLT LOGIC CELL A - NOT RECOMMENDED for NEW DESIGN FPGA, 600 CLBS, 100000 GATES, 263 MHz, PQFP144
30000 SYSTEM GATE 2.5 VOLT LOGIC CELL AR - NOT RECOMMENDED for NEW DESIGN FPGA, 216 CLBS, 30000 GATES, 263 MHz, PQFP100
150 000 SYSTEM GATE 2.5 VOLT FPGA (IQ AU - NOT RECOMMENDED for NEW DESIGN
15000 SYSTEM GATE 2.5 VOLT LOGIC CELL AR - NOT RECOMMENDED for NEW DESIGN
50000 SYSTEM GATE 2.5 VOLT LOGIC CELL AR - NOT RECOMMENDED for NEW DESIGN
Spartan-II FPGA Family
Second generation ASIC replacement technology
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| File Size |
937.07K /
99 Page |
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Download Datasheet |
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