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PHILIPS
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| Part No. |
74LVCH1624 74LVCH16245A 74LVC16245A
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| OCR Text |
...range from -40 to +85 C; note 2 VFBGA package Notes 1. The input and output voltage ratings may be exceeded if the input and output current ...56 balls; body 4.5 x 7 x 0.65 mm
SOT702-1
D
B
A
ball A1 index area
E
A
A2 A1... |
| Description |
16-bit bus transceiver with direction
pin; 5 V tolerant (3-state)
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| File Size |
103.93K /
20 Page |
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it Online |
Download Datasheet
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Cypress
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| Part No. |
CY7C68000A
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| OCR Text |
... options--56-pin QFN and 56-pin VFBGA All required terminations, including 1.5-Kohm pull-up on DPLUS, are internal to chip * Supports USB 2.0 test modes The Cypress MoBL-USB TX2 is a Universal Serial Bus (USB) specification revision 2.0 tra... |
| Description |
MoBL-USB TX2™ USB 2.0 UTMI Transceiver
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| File Size |
160.92K /
4 Page |
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it Online |
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Integrated Device Technology, Inc.
IDT[Integrated Device Technology]
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| Part No. |
IDT74AUCR16245 IDT74AUCR16245PFI IDT74AUCR16245BVI IDT74AUCR16245PAI
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| OCR Text |
... Available in TSSOP, TVSOP, and VFBGA packages
APPLICATIONS:
* High performance, low voltage communications systems * High performance...56 BALL VFBGA PACKAGE LAYOUT
A 6 5 4 3 2 1
B
C
D
E
F
G
H
J
K
TOP VI... |
| Description |
1.8V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS AUC SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48
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| File Size |
91.37K /
7 Page |
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it Online |
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Philips
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| Part No. |
74LVT16244B 74LVT16244BEV
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| OCR Text |
...4B
PIN CONFIGURATION 56-ball VFBGA terminal assignments
1 A B 2 3 4 5 6
PIN DESCRIPTION 56-ball VFBGA terminal assignments
1 A B 1OE 1Y1 1Y3 2Y1 2Y3 3Y0 3Y2 4Y0 4Y2 4OE 2 NC 1Y0 1Y2 2Y0 2Y2 3Y1 3Y3 4Y1 4Y3 NC GND VCC GND NC GND VCC ... |
| Description |
74LVT16244B; 3.3 V LVT 16-bit buffer/driver (3-State)
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| File Size |
104.52K /
12 Page |
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it Online |
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IDT
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| Part No. |
IDTCSPT857_A
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| OCR Text |
...able in 48-pin TSSOP and 56-pin VFBGA packages
The CSPT857 is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one... |
| Description |
2.5V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
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| File Size |
121.50K /
12 Page |
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it Online |
Download Datasheet |
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IDT
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| Part No. |
IDTCSPT857C
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| OCR Text |
...d TVSOP, 40-pin MLF, and 56-pin VFBGA packages
The CSPT857C is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and on... |
| Description |
2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
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| File Size |
135.63K /
15 Page |
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it Online |
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Philips
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| Part No. |
74LVT16374A 74LVT16374A_4
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| OCR Text |
... ASSIGNMENTS FOR 74LVT16374A IN VFBGA
1 A B C D E F G H J K 1 OEn 1Q1 1Q3 1Q5 1Q7 2Q0 2Q2 2Q4 2Q6 2OEn 2 NC 1Q0 1Q2 1Q4 1Q6 2Q1 2Q3 2Q5 2Q7...56 balls; body 4.5 x 7 x 0.65 mm
SOT702-1
2002 Nov 01
11
Philips Semiconductors
Produ... |
| Description |
3.3V LVT 16-bit edge-triggered D-type
From old datasheet system
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| File Size |
111.47K /
13 Page |
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it Online |
Download Datasheet |
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IDT
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| Part No. |
IDT74AUC16374 74AUC16374_DATASHEET
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| OCR Text |
... Available in TSSOP, TVSOP, and VFBGA packages
APPLICATIONS:
* high performance, low voltage communications systems * high performance...56 BALL VFBGA PACKAGE LAYOUT
A 6 5 4 3 2 1
B
C
D
E
F
G
H
J
K
TOP VI... |
| Description |
1.8V CMOS 16-BIT EDGETRIGGERED D-TYPE FLIP-FLOP
From old datasheet system
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| File Size |
89.65K /
8 Page |
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it Online |
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Price and Availability
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