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Xilinx, Inc.
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| Part No. |
XC2S15 XC2S50 XC2S30 XC2S150 XC2S100 XC2S200
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| OCR Text |
...ced pro- cess technology with a streamlined virtex-based architec- ture. features include block ram (to 56k bits), distributed ram (to 75,264 bits), 16 selectable i/o standards, and four dlls. fast, predictable interconnect means that succe... |
| Description |
Spartan-II 2.5V FPGA(Spartan-II 2.5V现场可编程门阵列)
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| File Size |
43.41K /
4 Page |
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it Online |
Download Datasheet
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Xilinx
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| Part No. |
XC2S200E
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| OCR Text |
...ced pro- cess technology with a streamlined architecture based on the proven virtex?-e platform. features include block ram (to 288k bits), distributed ram (to 221,184 bits), 19 select- able i/o standards, and four dlls (delay-locked loops)... |
| Description |
(XC2SxxxE) Spartan IIE 1.8V FPGA Family
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| File Size |
836.47K /
103 Page |
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it Online |
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Lineage Power
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| Part No. |
ORT4622
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| OCR Text |
...bling/descrambling of data and streamlined sonet framing, pointer moving, and transport overhead handling, plus the programmable logic to terminate the network into proprietary sys- tems. for non-sonet applications, all sonet func- tiona... |
| Description |
Field-Programmable System Chip (FPSC) Four Channel x 622 Mbits/s Backplane Transceiver(现场可编程系统芯片（四通道x 622 M秒背板收发器
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| File Size |
124.48K /
6 Page |
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it Online |
Download Datasheet |
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AGERE[Agere Systems]
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| Part No. |
TTSV02622 TTSV02622V2-DB
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| OCR Text |
...cation via the TOH serial link. streamlined pointer processor (pointer mover) for 8 kHz frame alignment. FIFOs for alignment of incoming data to reference clock. FIFOs optionally align incoming data across all two channels for synchronous t... |
| Description |
STS-24 Backplane Transceiver
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| File Size |
641.04K /
64 Page |
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it Online |
Download Datasheet |
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Xilinx
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| Part No. |
XC2S400E6FXXX
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| OCR Text |
...anced process technology with a streamlined architecture based on the proven VirtexTM-E platform. Features include block RAM (to 288K bits), distributed RAM (to 221,184 bits), 19 selectable I/O standards, and four DLLs (Delay-Locked Loops).... |
| Description |
Spartan-IIE 1.8V FPGA Family
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| File Size |
780.94K /
103 Page |
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it Online |
Download Datasheet |
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Price and Availability
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