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Part No. |
MT8VDDT1664AG-202A1
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OCR Text |
...v dd q = +2.5v 0.2v 2.5v i/o (sstl_2 compatible) commands entered on each positive ck edge dqs edge-aligned with data for reads; center- aligned with data for writes internal, pipelined double data rate (ddr) architecture; two data ... |
Description |
16M X 64 DDR DRAM MODULE, 0.8 ns, DMA184
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File Size |
403.49K /
23 Page |
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it Online |
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NANYA TECHNOLOGY CORP
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Part No. |
NT5DS128M4BT-6K
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OCR Text |
...riodic refresh interval ? 2.5v (sstl_2 compatible) i/o ?v dd = v ddq = 2.5v 0.2v (6k & 75b) ?v dd = v ddq = 2.6v 0.1v (5t) description nt5ds128m4bf, nt5ds128m4bt, nt5ds128m4bg, nt5ds128m4bs, nt5ds64m8bf, nt5ds64m8bt, nt5ds64m8bg... |
Description |
128M X 4 DDR DRAM, 0.7 ns, PDSO66
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File Size |
2,500.58K /
80 Page |
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it Online |
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HYNIX SEMICONDUCTOR INC
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Part No. |
HY5DU561622ELTP-L
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OCR Text |
...tage levels are compatible with sstl_2. features ?v dd , v ddq = 2.5v +/- 0.2v for ddr200, 266, 333 v dd , v ddq = 2.6v +0.1v / -0.2v for ddr400 ? all inputs and outputs are compatible with sstl_2 interface ? fully differential clock ... |
Description |
16M X 16 DDR DRAM, 0.75 ns, PDSO66
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File Size |
235.08K /
29 Page |
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it Online |
Download Datasheet
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HYNIX SEMICONDUCTOR INC
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Part No. |
HY5DU561622ELTP-JI
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OCR Text |
...tage levels are compatible with sstl_2. features ?v dd , v ddq = 2.5v +/- 0.2v for ddr200, 266, 333 v dd , v ddq = 2.6v +0.1v / -0.2v for ddr400 ? all inputs and outputs are compatible with sstl_2 interface ? fully differential clock ... |
Description |
16M X 16 DDR DRAM, 0.7 ns, PDSO66
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File Size |
235.26K /
29 Page |
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it Online |
Download Datasheet
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Price and Availability
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