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Nanya Techology
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Part No. |
NT5DS32M4AT
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OCR Text |
...s is edge-aligned with data for reads and is center- aligned with data for writes ? differential clock inputs (ck and ck ) ? four internal banks for concurrent operation ? data mask (dm) for write data ? dll aligns dq and dqs transitions w... |
Description |
(NT5DS16M8AT / NT5DS32M4AT) 128Mb DDR SDRAM
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File Size |
1,559.58K /
76 Page |
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it Online |
Download Datasheet
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INTEGRATED DEVICE TECHNOLOGY INC IDT[Integrated Device Technology]
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Part No. |
IDT71V509S66Y IDT71V509 IDT71V509S50Y
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OCR Text |
... turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM , or Zero Bus TurnaroundTM . Addresses and control signals are applied to the SRAM
during one clock cycle, and one clock cycle ... |
Description |
128K x 8 3.3V SYNCHRONOUS SRAM WITH ZBTO AND FLOW-THROUGH OUTPUT
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File Size |
94.81K /
9 Page |
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it Online |
Download Datasheet
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Price and Availability
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