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Cypress Semiconductor Corp.
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| Part No. |
CY7C1350 7C1350
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| OCR Text |
... by the four Byte Write Select (bws[3:0]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) pro... |
| Description |
128Kx36 Pipelined SRAM with NoBL Architecture(带NoBL结构28Kx36流水线式 SRAM) 128K × 36至流水线与总线延迟静态存储器体系结构（带总线延迟结构28K × 36至流水线式的SRAM
128Kx36 Pipelined SRAM with NoBL Architecture(B>NoBL结构28Kx36流水线式 SRAM)
From old datasheet system
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| File Size |
185.89K /
13 Page |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1345 7C1345
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| OCR Text |
...V ADSC ADSP A[16:0] GW BWE bws3 bws 2 bws 1 bws 0 CE1 CE2 CE3
MODE (A0,A1) 2 BURST Q0 CE COUNTER Q1 CLR Q ADDRESS CE REGISTER D DDQ[31:24],DP3Q BYTEWRITE REGISTERS DDQ[23:16],DP2Q BYTEWRITE REGISTERS D DQ[15:8],DP1 Q BYTEWRITE REGISTERS ... |
| Description |
128K x 36 Synchronous Flow-Through 3.3V Cache RAM(3.3V 128K x 36 同步流通式高速缓冲RAM) 128K的36同步流动，通过3.3V的高速缓存内存（3.3 128K的36同步流通式高速缓冲内存）
From old datasheet system
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| File Size |
272.33K /
16 Page |
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it Online |
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Cypress
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| Part No. |
CY7C1302V25 7C1302V25
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| OCR Text |
...4 Q14 D15 D16 Q16 Q17 A 4 WPS 5 bws 1 NC A VSS VSS VDD VDD VDD VDD VSS VSS VSS A A A 6 K 7 NC 8 RPS 9
CY7C1302V25
10 Gnd/ 72M NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS
11 NC
NC/ 18M NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A
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| Description |
9-Mb Pipelined SRAM with QDR?Architecture
From old datasheet system
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| File Size |
249.54K /
23 Page |
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it Online |
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Cypress
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| Part No. |
CY7C1304V25 7C1304V25
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| OCR Text |
...eg. 36 Reg. 18 Reg.
Vref WPS bws[0:1]
18 Q [17:0]
Selection Guide
7C1304V25-167 Maximum Operating Frequency (MHz) Maximum Operating Current (mA) 167 450 7C1304V25-133 133 350 7C1304V25-100 100 230
Cypress Semiconductor Corporat... |
| Description |
9-Mb Pipelined SRAM with QDR?Architecture
From old datasheet system
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| File Size |
215.62K /
23 Page |
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it Online |
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Cypress
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| Part No. |
CY7C1355V25 CY7C1357V25 7C1355V
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| OCR Text |
...
DQx DPx
CY7C1355 AX DQX DPX bws X X = 17:0 X= a, b, c, d X = a, b, c, d X = a, b, c, d
CY7C1357 X = 18:0 X = a, b X = a, b X = a, b
OE
Selection Guide
7C1355V25-133 7C1357V25-133 Maximum Access Time (ns) Maximum Operating Curr... |
| Description |
256Kx36/512Kx18 Flow-Thru SRAM with NoBL Architecture
From old datasheet system
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| File Size |
334.51K /
26 Page |
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it Online |
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Cypress Semiconductor Corp.
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| Part No. |
CY7C1353 7C1353
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| OCR Text |
... by the four Byte Write Select (bws[1:0]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) pro... |
| Description |
256Kx18 Flow-Through SRAM with NoBL Architecture(B>NoBL结构56Kx18流通式 静态RAM)
From old datasheet system
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| File Size |
180.62K /
12 Page |
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Cypress
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| Part No. |
CY7C1325 7C1325
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| OCR Text |
...tions
100-Lead TQFP
OE ADSC bws 1 bws 0 ADSP ADV 84 83 BWE
CE1
CE2
CE3
VDD
CLK
VSS
GW
NC
NC
A6
A7
A8 82
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85... |
| Description |
256K x 18 Synchronous3.3V Cache RAM
From old datasheet system
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| File Size |
264.13K /
15 Page |
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it Online |
Download Datasheet |
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