|
|
 |
ALTERA
|
Part No. |
EP20K100EQ EP20K100QC EP20K100EQC240-2
|
OCR Text |
...T, stubseries terminated logic (SSTL-3 and sstl-2), Gunning transceiver logic plus (GTL+), and high-speed terminated logic (HSTL Class I) - Pull-up on I/O pins before and during configuration Advanced interconnect structure - Four-level hie... |
Description |
Apex 20KE Device Family (1.8V, LVDS Apex 20K Device Family (2.5V)
|
File Size |
585.74K /
116 Page |
View
it Online |
Download Datasheet
|
|
|
 |
NANYA TECHNOLOGY CORP
|
Part No. |
NT512D64SH8B0GN-75B
|
OCR Text |
...ions inputs and outputs are sstl-2 compatible v dd = v ddq = 2.5v 0.2v sdrams have 4 internal banks for concurrent operation differential clock inputs data is read or written on both clock edges dram dll aligns dq ... |
Description |
64M X 64 DDR DRAM MODULE, 0.75 ns, DMA200
|
File Size |
508.34K /
18 Page |
View
it Online |
Download Datasheet
|
|

Price and Availability
|