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Motorola
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Part No. |
MPC755CD MPC755CE
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OCR Text |
... L2CR clock stop bit to put the SRAMs into a ZZ for same low power. power mode during sleep. PB3: None exists. PB3: Cannot use as ADS pin for this type of SRAM. L2 address parity cannot be None used. Y Y Y Systems requiring the ability to p... |
Description |
RISC Microprocessor Chip Errata
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File Size |
81.17K /
12 Page |
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CYPRESS SEMICONDUCTOR CORP
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Part No. |
MT55L512V18FF-11 MT55L512V18FF-12 MT55L256L36FT-10 MT55L256L36FT-11 MT55L256L36FF-11
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OCR Text |
... cmos process. micron?s 8mb zbt srams integrate a 512k x 18, 256k x 32, or 256k x 36 sram core with advanced synchronous peripheral circuitry and a 2-bit burst counter. these srams are optimized for 100 percent bus utilization, eliminating ... |
Description |
512K X 18 ZBT SRAM, 8.5 ns, PBGA165 512K X 18 ZBT SRAM, 9 ns, PBGA165 256K X 36 ZBT SRAM, 7.5 ns, PQFP100 256K X 36 ZBT SRAM, 8.5 ns, PQFP100 256K X 36 ZBT SRAM, 8.5 ns, PBGA165
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File Size |
293.36K /
25 Page |
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it Online |
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GSI Technology, Inc.
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Part No. |
GS8180S18
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OCR Text |
...d for separate i/o synchronous srams. they are 18,874,368-bit (16mb) srams. these are the first in a family of wide, very low voltage cmos i/o srams designed to operate at the speeds needed to implement economical high performance net... |
Description |
1Mb x 18Bit Separate I/O Sigma DDR SRAM(1M x 18位独立I/O接口双数据速率读和写模式静态ΣRAM) 1x 18位独立的I / O西格玛的DDR SRAM的(100万18位独立的I / O接口双数据速率读和写模式静态ΣRAM
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File Size |
859.07K /
32 Page |
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it Online |
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GSI Technology, Inc.
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Part No. |
GS8170S18
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OCR Text |
...pinout standard for synchronous srams. they are 18,874,368-bit (16mb) srams. these are the first in a family of wide, very low voltage cmos i/o srams designed to operate at the speeds needed to implement economical high performance net... |
Description |
16MbM x 18Bit)Synchronous SRAM(16M位(1M x 18位)同步静态RAM) 16Mb的(100x 18位)同步SRAM,600位(100万18位)同步静态内存)
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File Size |
944.05K /
38 Page |
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it Online |
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Price and Availability
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