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IDT
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| Part No. |
IDT82V2108PX8
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| OCR Text |
...s up to three internal floating hdlc controllers for each framer to support isdn pri and v5.x interface. each hdlc con- tains 128-byte deep fifos in both the receive and transmit direc- tions ? provides jitter attenuation performance exceed... |
| Description |
8 Channel T1/J1/E1 Framer
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| File Size |
1,190.86K /
272 Page |
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it Online |
Download Datasheet
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Maxim
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| Part No. |
DS21Q55
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| OCR Text |
...l- less jitter attenuator Dual hdlc controllers On-chip programmable BERT generator and detector Internal software-selectable receive and transmit side termination resistors Dual two- frame elastic-store slip buffers to interface backpl... |
| Description |
Quad T1/E1/J1 Transceiver
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| File Size |
3,260.99K /
248 Page |
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it Online |
Download Datasheet |
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Motorola
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| Part No. |
MC68SC302
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| OCR Text |
...). Each SCC can support onboard hdlc processing as well as totally transparent operation. The dual-port RAM provides 1536 bytes of memory. A maximum of 1280 bytes can be allocated for serial channel buffer space, which, when allocated evenl... |
| Description |
APPLICATION DEVELOPMENT SYSTEM
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| File Size |
43.00K /
8 Page |
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it Online |
Download Datasheet |
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PMC-Serria
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| Part No. |
PM6344
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| OCR Text |
...elected channels. * Provides an hdlc interface for terminating/generating a datalink. * Optionally extracts the datalink from timeslot 16 or from any combination of the national bits. * Software and functionally compatible with the PM6341 E... |
| Description |
Quad E1 Framer
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| File Size |
98.88K /
2 Page |
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it Online |
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Maxim Integrated Products, Inc.
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| Part No. |
DS33X162
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| OCR Text |
...psulating mac frames in gfp-f, hdlc, chdlc, or x.86 (laps) for transmission over pdh/tdm data streams. the devices suppor t the ethernet over pdh (eopdh) standards for t he delivery of ethernet access services, including elan, eline, a... |
| Description |
Ethernet Over PDH Mapping Devices DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PBGA256
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| File Size |
2,661.10K /
375 Page |
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it Online |
Download Datasheet |
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Maxim Integrated Products, Inc.
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| Part No. |
DS21Q42TN
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| OCR Text |
...eive functionality integral hdlc controller with 64-byte buffers configurable for fdl or ds0 operation generates and detects in-band loop codes from 1 to 8 bits in length including csu loop codes pin compatible with ds21q44 e1 ... |
| Description |
Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 DATACOM, FRAMER, PQFP128
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| File Size |
971.32K /
116 Page |
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it Online |
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Infineon
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| Part No. |
SAB82538 SAB8258K
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| OCR Text |
...r oriented (MONOSYNC BISYNC) or hdlc/SDLC modes (including SDLC LOOP) * Transparent receive/transmit of data bytes without framing * NZR, NRZI, FM and Manchester encoding * Modem control lines (RTS, CTS, CD) * CRC support: - hdlc/SDLC: CRC-... |
| Description |
Enhanced Serial Communication Controller (ESCC8)
From old datasheet system
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| File Size |
16.34K /
2 Page |
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it Online |
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BI Technologies, Corp.
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| Part No. |
DS21FT40
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| OCR Text |
...d h12 applications ? integral hdlc controller with 64-byte buffers. configurable for sa bits or ds0 operation ? detects and generates ais, remote alarm, and remote multiframe alarms ? ieee 1149.1 support description the ds21ft40 mcm ... |
| Description |
Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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| File Size |
399.93K /
87 Page |
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it Online |
Download Datasheet |
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pmc
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| Part No. |
1991437
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| OCR Text |
... the text. Change to Section 1: hdlc interface with 127 bytes of buffering for terminating the facility data link. Change to Section 1: Seamlessly interfaces with 77.76 MHz Drop and 77.76 MHz Add buses. New: Figure 1 Fractional DS3 Applicat... |
| Description |
From old datasheet system
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| File Size |
2,868.88K /
317 Page |
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it Online |
Download Datasheet |
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