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  dpll Datasheet PDF File

For dpll Found Datasheets File :: 724    Search Time::2.125ms    
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    Fujitsu Limited
Part No. MB86H21
OCR Text ...n integrated S/P-DIF interface, dpll, and internal audio DAC's. This helps to reduce product cost by eliminating the need for external components. The SmartMPEG adds also NDS support, dpll functionality, SECAM encoding, and two Smart-card i...
Description MPEG-2 Decoder with Integrated NDS ICAM

File Size 163.01K  /  3 Page

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    ZARLINK[Zarlink Semiconductor Inc]
Part No. ZL30122 ZL30122GGG ZL30122GGG2
OCR Text ... kHz Digital Phase Locked-Loop (dpll) provides all the features necessary for generating SONET/SDH compliant clocks including automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), and selectable loop ...
Description From old datasheet system
SONET/SDH Low Jitter Line Card Synchronizer

File Size 250.01K  /  23 Page

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    Zarlink Semiconductor
Part No. ZL30102
OCR Text ...Circuit Virtual Reference dpll Mode Control E1 Synthesizer DS1 Synthesizer DS2 Synthesizer Frequency Select MUX IEEE 1149.1a TRST MODE_SEL1:0 SEC_MSTR HMS HOLDOVER TCK TDI TMS TDO Figure 1 - Functional B...
Description Stratum 4/4E Redundant System Clock Synchronizer for T1/E1 and H.110

File Size 457.90K  /  50 Page

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    PMC-Sierra, Inc.
Part No. PM4541
OCR Text .......................... 3 CLOCK dpll ................................................................................ 3 OSCILLATORS.............................................................................. 3 T1XC DEVICES ..................
Description T1XC EVALUATION DAUGHTER BOARD

File Size 525.44K  /  46 Page

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    9290X01

Samsung Semiconductor
Part No. 9290X01
OCR Text ... processing, wide capture range dpll and 1-bit DAC for the CD player are installed in S5L9290X. FEATURES * Signal processing part -- EFM data demodulation -- Frame sync detection, protection, insertion -- Sub code data processing (Q dat...
Description Search --To S5L9290X01

File Size 326.04K  /  48 Page

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    Zarlink
Part No. MT8940 118
OCR Text ...k and frame pulse source F0i dpll #1 C12i 2:1 MUX CVb Variable Clock Control CV ENCV MS0 MS1 MS2 MS3 C8Kb Mode Selection Logic Frame Pulse Control Input Selector 4.096 MHz Clock Control dpll #2 Clock Generator Ai Bi 2.048 MHz Clock...
Description ISO-CMOS ST-BUS? FAMILY
From old datasheet system

File Size 492.69K  /  19 Page

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    T8100A T8105A T8102A

AGERE[Agere Systems]
Part No. T8100A T8105A T8102A
OCR Text ...r 4.096 MHz in the digital PLL (dpll). The dpll introduces sufficient jitter on the A or B master output clocks that slave devices falsely interpret as a loss of sync and either snap or slide align to this false sync indication. This, in tu...
Description H.100/H.110 Interface and Time-Slot Interchangers

File Size 1,337.82K  /  112 Page

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    Maxim Integrated Products, Inc.
Part No. DS3104-SE
OCR Text .......11 TIMING CARD TO LINE CARD dpll FEATURES (T0 dpll)..............................................................11 LINE CARD TO TIMING CARD dpll FEATURES (T4 dpll)..............................................................11 OUTPUT ...
Description Line Card Timing IC with Synchronous Ethernet Support

File Size 1,029.11K  /  135 Page

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