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Alliance Semiconductor Corp...
Alliance Semiconductor, Corp.
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| Part No. |
AS7C33256PFD32A-166TQIN AS7C33256PFD32A-133TQCN AS7C33256PFD36A-133TQCN
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| OCR Text |
... . in a read operation the data acce ssed by the current address, regist ered in the address registers by the positive edge of clk, are carried to the data-out registers a nd driven on the output pins on the next positive edge of clk. adv... |
| Description |
3.3V 256K x 32/36 pipelined burst synchronous SRAM 256K X 32 STANDARD SRAM, 4 ns, PQFP100
3.3V 256K x 32/36 pipelined burst synchronous SRAM 3.3 256 × 32/36管线爆裂同步SRAM
3.3V 256K x 32/36 pipelined burst synchronous SRAM 256K X 32 STANDARD SRAM, 3.5 ns, PQFP100
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| File Size |
511.39K /
20 Page |
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it Online |
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Alliance Semiconductor, Corp.
Alliance Semiconductor Corp...
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| Part No. |
AS7C33512PFD18A-133TQCN AS7C33512PFD18A-133TQIN AS7C33512PFD18A-166TQC AS7C33512PFD18A-166TQIN
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| OCR Text |
...-mbit synchronous static random acce ss memory (sram) devices organized as 524,288 words 18 bits and incorporate a pipeli ne for highest frequency on any given technology. fast cycle times of 6/7.5 ns with clock access times (t cd ) of 3.... |
| Description |
3.3V 512K x 18 pipeline burst synchronous SRAM 512K X 18 STANDARD SRAM, 4.5 ns, PQFP100
3.3V 512K x 18 pipeline burst synchronous SRAM 512K X 18 STANDARD SRAM, 4 ns, PQFP100
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| File Size |
498.97K /
20 Page |
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Qimonda
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| Part No. |
HYB25DC512160B
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| OCR Text |
...tiated at the end of the burst acce ss. as with standard sdrams, the pipelined, multibank architecture of ddr sdrams allows for concurrent operation, ther eby providing high effective bandwidth by hiding row precharge and activation time.... |
| Description |
512-Mbit Double-Data-Rate SDRAM
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| File Size |
1,168.00K /
35 Page |
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NEC, Corp.
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| Part No. |
UPD72852AGB-8EU
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| OCR Text |
...eed concatenation, arbitration acce leration, fly-by concatenation ? suspend debounce timer for esd ? ?bias detected? signal output ? double speed signal filter for bias ringing ? small package: 64-pin plastic lqfp ? super low po... |
| Description |
IEEE1394a-2000 COMPLIANT 400 Mbps TWO-PORT PHY LSI 1个IEEE1394a 2000年的要求400 Mbps的双端口PHY的大规模集成电路
2 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP64
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| File Size |
360.27K /
48 Page |
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it Online |
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