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Integrated Device Technology, Inc.
INTEGRATED DEVICE TECHNOLOGY INC
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| Part No. |
ICS9112YM-17LF-T
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| OCR Text |
...er. it uses a phase lock loop (pll) technology to align, in both phase and frequency, the ref input with the clkout signal. it is designed to distribute high speed clocks in pc systems operating at speeds from 25 to 133 mhz. ics9112-17 i... |
| Description |
9112 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 0.150 INCH, ROHS COMPLIANT, MS-012, SOIC-16
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| File Size |
136.22K /
9 Page |
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Integrated Device Technology, Inc.
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| Part No. |
ICS8430DYI-11LFT ICS8430DYI-11T
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| OCR Text |
...s_clock np_load m0:m8 n0:n2 vco pll fout0 nfout0 fout1 nfout1 test n configuration interface logic m 0 1 0 1 16 phase detector mr 2
...frequency characteristics, table 5, note 1. the ics8430i-11 features a fully integrated pll and ther... |
| Description |
700 MHz, OTHER CLOCK GENERATOR, PQFP32 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32
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| File Size |
169.70K /
16 Page |
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Integrated Device Technology, Inc.
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| Part No. |
ICS810252AYI-03LFT ICS810252AYI-03T
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| OCR Text |
...rom idt. the ics810252i-03 is a pll based synchronous multiplier that is optimized for pdh or sonet to ethernet clock jitter attenuation and frequency translation. the device contains two internal frequency multiplication stages that are ca... |
| Description |
156.25 MHz, OTHER CLOCK GENERATOR, PQFP32 7 X 7 MM, 1 MM HEIGHT, ROHS COMPLIANT, MS-026ABA-HD, TQFP-32
156.25 MHz, OTHER CLOCK GENERATOR, PQFP32 7 X 7 MM, 1 MM HEIGHT, MS-026ABA-HD, TQFP-32
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| File Size |
378.40K /
19 Page |
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PhaseLink, Corp.
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| Part No. |
CY28325OC-3 CY28325OC-3T
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| OCR Text |
...configuration vdd_ref xtal pll ref freq x2 x1 vdd_pci osc sclk pll 1 smbus logic vdd_48mhz sdata vdd_agp divider network vdd_cpu (3.3v)...frequency input: this pin has dual functions. it can be used as an external 14.318-mhz crystal co... |
| Description |
200.5 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 SSOP-48
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| File Size |
186.45K /
18 Page |
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Cypress Semiconductor, Corp.
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| Part No. |
CY28351OI-400
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| OCR Text |
... frequency ? phase-locked loop (pll) clock distribution for double data rate synchronous dram applications ? distributes one clock input to...frequency affects the static phase offset of the pll and thus the relative delay between the inputs ... |
| Description |
PLL BASED CLOCK DRIVER, PDSO48 SSOP-48
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| File Size |
127.29K /
7 Page |
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Integrated Device Technology, Inc.
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| Part No. |
9UMS9001YKLF-T
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| OCR Text |
...v power supply for the 48/96mhz pll 19 vddio_96mhz pwr power supply for dot96 output. vdd_io = 1.05 to 3.3v +/-5%. 20 dot96c_lprs out compl...frequency select input. see table 1: cpu frequency select table and the vih_fs and vil_fs specifi... |
| Description |
200 MHz, PROC SPECIFIC CLOCK GENERATOR, PQCC14 ROHS COMPLIANT, PLASTIC, MLF-56
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| File Size |
112.82K /
15 Page |
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it Online |
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