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Zarlink Semiconductor
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| Part No. |
ZL50015
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| OCR Text |
...ated digital phase-locked loop (dpll) exceeds telcordia gr-1244-core stratum 4e specifications ? output clocks have less than 1 ns of jitter (except for the 1.544 mhz output) ? dpll provides holdover, freerun and jitter attenuation feat... |
| Description |
Enhanced 1 K Channel TDM Switch with Stratum 4E dpll
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| File Size |
733.17K /
114 Page |
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IDT
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| Part No. |
IDT82V3155PV8
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| OCR Text |
...uit 1 f1_sel0 f1_sel1 c32o c19o dpll c2/c1.5 features ? supports at&t tr62411 and te lcordia gr-1244-core stratum 3, stratum 4 enhanced and stra tum 4 clock, oc-3 port and 155.52 mbit/s application ? supports itu-t g.813 option 1 clocks ? s... |
| Description |
T1/E1/OC3(155M) WAN PLL, Dual Input Reference. Stratum 3/4/4E
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| File Size |
383.51K /
30 Page |
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IDT
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| Part No. |
IDT82V3012PV
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| OCR Text |
...uit 1 f1_sel0 f1_sel1 c32o c19o dpll c2/c1.5 features ? supports at&t tr62411 and te lcordia gr-1244-core stratum 3, stratum 4 enhanced and stra tum 4 timing for ds1 interfaces ? supports itu-t g.813 option 1 clocks ? supports itu-t g.812 t... |
| Description |
T1/E1/OC3(19.44M) WAN PLL, Dual Input Reference. Stratum 3/4/4E
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| File Size |
370.99K /
31 Page |
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it Online |
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Samsung
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| Part No. |
S5L9290X01S5L9290X02 S5L9290
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| OCR Text |
... processing, wide capture range dpll and 1-bit DAC for the CD player are installed in S5L9290X.
FEATURES
* Signal processing part -- EFM data demodulation -- Frame sync detection, protection, insertion -- Sub code data processing (Q dat... |
| Description |
Processor Miscellaneous
From old datasheet system
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| File Size |
265.83K /
48 Page |
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Zarlink
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| Part No. |
MT8941B 119
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| OCR Text |
...k and frame pulse source
F0i dpll #1 C12i 2:1 MUX
Variable Clock Control
CVb CV ENCV
MS0 MS1 MS2 MS3 C8Kb Mode Selection Logic Frame Pulse Control Input Selector 4.096 MHz Clock Control dpll #2 F0b
C4b C4o ENC4o C2o C2o ENC2o... |
| Description |
Advanced T1/CEPT Digital Trunk PLL
From old datasheet system
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| File Size |
604.46K /
29 Page |
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it Online |
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Zarlink Semiconductor Inc.
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| Part No. |
ZL30409/DDB ZL30409/DDA
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| OCR Text |
...ns a digital phase-locked loop (dpll), which provides timing and synchronization signals for multitrunk t1 and e1 primary rate transmission links. the zl30409 generates st-bus clock and framing signals that are phase locked to either a 19.4... |
| Description |
T1/E1 System Synchronizer with Stratum 3 Holdover
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| File Size |
290.90K /
32 Page |
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it Online |
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Zarlink Semiconductor Inc.
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| Part No. |
MT8941B MT8941BP MT8941BPR1 MT8941BP1
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| OCR Text |
...ck control mode selection logic dpll #2 input selector clock generator frame pulse control 4.096 mhz clock control 2.048 mhz clock control dpll #1
mt8941b data sheet 2 zarlink semiconductor inc. figure 2 - pin connections pin description ... |
| Description |
Advanced T1/CEPT Digital Trunk PLL
Round Conductor Flat Cable, 3849/96 30 AWG, .033 (0.85)
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| File Size |
484.51K /
27 Page |
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it Online |
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